ICS8741004I

DIFFERENTIAL-TO-LVDS/0.7V DIFFERENTIAL PCI EXPRESS™ JITTER ATTENUATOR

PRELIMINARY

IDT™ / ICS™ PCI EXPRESS™ JITTER ATTENUATOR

3

ICS8741004BGI REV. B SEPTEMBER 27, 2007

Table 1. Pin Descriptions

NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.

Table 2. Pin Characteristics

Number

Name

Type

Description

1, 24

nQA1, QA1

Output

Differential output pair. LVDS interface levels.

3, 22

Power

Output supply pins.

4, 5

QA0, nQA0

Output

Differential output pair. LVDS interface levels.

6

MR

Input

Pulldown

Active High Master Reset. When logic HIGH, the internal dividers are reset

causing the true outputs Q[Ax:Bx] to go LOW and the inverted outputs

nQ[Ax:Bx] to go HIGH. When logic LOW, the internal dividers and the outputs

are enabled. LVCMOS/LVTTL interface levels.

7

BW_SEL

Input

Pullup/

Pulldown

PLL Bandwidth input. LVCMOS/LVTTL interface levels. See Table 3B.

8

nc

Unused

No connect.

Power

Analog supply pin.

10

F_SELA

Input

Pulldown

Frequency select pins for QAx/nQAx outputs.

LVCMOS/LVTTL interface levels. See Table 3C.

11

Power

Core supply pin.

12

OEA

Input

Pullup

Output enable for QAx pins. When HIGH, QAx/nQAx outputs are enabled.

When LOW, the QAx/nQAx outputs are in a high impedance state.

LVCMOS/LVTTL interface levels. See Table 3A.

13

CLK

Input

Pulldown

Non-inverting differential clock input.

14

nCLK

Input

Pullup

Inverting differential clock input.

15, 16

GND

Power

Power supply ground.

17

OEB

Input

Pullup

Output enable for QBx pins. When HIGH, QBx/nQBx outputs are enabled.

When LOW, the QBx/nQBx outputs are in a high impedance state.

LVCMOS/LVTTL interface levels. See Table 3A.

18

F_SELB

Input

Pulldown

Frequency select pins for QBx/nQBx outputs.

LVCMOS/LVTTL interface levels. See Table 3C.

19

IREF

Input

A fixed precision resistor (RREF = 475

reference current used for differential current-mode QB0/nQB0 clock outputs.

20, 21

nQB0, QB0

Output

Differential output pair. HCSL interface levels.

23, 24

QB1, nQB1

Output

Differential output pair. HCSL interface levels.

Symbol

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

Input Capacitance

4

pF

Input Pullup Resistor

51

k

Ω

51

k

Ω