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HCF4029BM1 Datasheet(PDF) 6 Page - STMicroelectronics |
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HCF4029BM1 Datasheet(HTML) 6 Page - STMicroelectronics |
6 / 13 page DYNAMIC ELECTRICAL CHARACTERISTICS (Tamb =25 oC, CL =50 pF, RL = 200 K Ω, typical temperature coefficent for all VDD values is 03 %/ oC, all input rise and fall times= 20 ns) Symbol Parameter Test Conditions Value Unit VDD (V) Min. Typ. Max. tPLH tPHL Propagation Delay Time (Q Outputs) 5 250 500 ns 10 120 240 15 90 180 tPLH tPHL Propagation Delay Time (Carry Output) 5 280 560 ns 10 130 260 15 95 190 tTLH tTHL Transition Time (Q Outputs, Carry Output) 5 100 200 ns 10 50 100 15 40 80 tW Minimum Clock Pulse Width 5 90 180 ns 10 45 90 15 30 60 tr,tf ** Clock Rise and Fall Time 5 15 µs 10 15 15 15 tsetup * Minimum Setup Time (Carry Input) 5 30 60 ns 10 10 20 15 6 12 tsetup Minimum Setup Time (B/D or UD) 5 170 340 10 70 140 15 50 100 fmax Maximum Clock Input Frequency 5 2 4 MHz 10 4 8 15 5.5 11 PRESET ENABLE tPLH tPHL Propagation Delay Time (Q Outputs) 5 235 470 ns 10 100 200 15 80 160 tPLH tPHL Propagation Delay Time (Carry Output) 5 320 640 10 145 290 15 105 210 tW Minimum Preset Enable (Pulse Width) 5 65 130 ns 10 35 70 15 25 50 trem * Minimum Preset Enable (Removal Time) 5 100 200 ns 10 55 110 15 40 80 CARRY INPUT tPHL tPLH Propagation Delay Time (Carry Output) 5 170 340 ns 10 70 140 15 50 100 tsetup *** Minimum Setup Time (Carry In) 5 25 50 ns 10 15 30 15 12 25 thold Minimum Hold Time (Carry In) 5 100 200 10 35 70 15 30 60 * From Up/Down, Binary/Decade, Carry In or Preset Enable Control Inputs to Clock Edge ** If more than one unit is cascated in the parallel clocked application tr should be made less than or equal to the sum of the fixed propagation delay at 15 pF and the transition time of the carry output driving stage for the estimated capacitance load. *** From Carry in to Clock Edge. HCC/HCF4029B 6/13 |
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