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TH8061 Datasheet(PDF) 8 Page - Melexis Microelectronic Systems |
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TH8061 Datasheet(HTML) 8 Page - Melexis Microelectronic Systems |
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8 / 36 page  TH8061 Voltage Regulator with integrated LIN Transceiver 2.4 Dynamic Characteristics 7V ≤ VSUP ≤ 18V, -40°C ≤ TA ≤ 125°C, unless otherwise specified Parameter Symbol Condition Min Typ Max Unit RESET Reset time tRes 70 100 140 ms Reset rising time [1] trr 3.0 7.5 15 µs Debouncing time BUS [1] tdeb_BUS 1.5 2.8 4.0 µs Wake up time twake_BUS 25 60 120 µs General LIN BUS parameter Transmit propagation delay TxD -> BUS [2] [3] tdr_TXD, tdf_TXD RL/CL at BUS 1k Ω/1nF 660 Ω/6.8nF 500 Ω/10nF 4 µs Symmetry of propagation delay BUS -> RxD [2] tdsym_TXD tdr_TXD - tdf_TXD -2 2 µs Receiver propagation delay BUS -> RxD [2] [3] tdr_RXD tdf_RXD CL(RXD) = 50pF 6 µs Symmetry of propagation delay TxD -> BUS [2] tdsym_RXD tdr_RXD - tdf_RXD -2 2 µs Slew rate BUS rising edge [1] dV/dTrise 20% ≤ VBUS ≤ 80% CBUS = 100 pF 1.0 1.7 2.5 V/ µs Slew rate BUS falling edge [1] dV/dTfall 20% ≤ VBUS ≤ 80% 100pF ≤ CBUS ≤ 10nF -2.5 -1.7 -1.0 V/ µs LIN BUS parameter according to LIN Spec. Rev. 1.3 VSUP = 8 V RL= 500 Ω / CL=10nF 12 Slope time, transition from recessive to dominant [2] [3] tsdom VSUP = 18 V RL= 500 Ω / CL=10nF 18 µs VSUP = 8 V RL= 500 Ω / CL=10nF 12 Slope time, transition from dominant to recessive [2] [3] tsrec VSUP = 18 V RL= 500 Ω / CL=10nF 18 µs VSUP = 8 V RL= 500 Ω / CL=10nF Tssym = tsdom - tsrec -7 1 Slope time symmetry tssym VSUP = 18 V RL= 500 Ω / CL=10nF Tssym = tsdom - tsrec -5 5 µs TH8061 – Datasheet Page 8 of 36 3901008061 June 2004 Rev 007 |
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