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FMA246 Datasheet(PDF) 2 Page - Filtronic Compound Semiconductors |
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FMA246 Datasheet(HTML) 2 Page - Filtronic Compound Semiconductors |
2 / 5 page Preliminary specifications subject to change without notice Filtronic Compound Semiconductors Ltd Tel: +44 (0) 1325 301111 Fax: +44 (0) 1325 306177 Email: sales@filcs.com Website: www.filtronic.com FMA246 Preliminary Datasheet v3.0 ABSOLUTE MAXIMUM RATING1: Notes: 1TAmbient = 22°C unless otherwise noted; exceeding any one of these absolute maximum ratings may cause permanent damage to the device 2Total Power Dissipation defined as: PTOT ≡ (PDC + PIN) – POUT, where PDC: DC Bias Power, PIN: RF Input Power, POUT: RF Output Power 3Total Power Dissipation to be de-rated as follows above 22°C: PTOT= 1.4 - (0.004W/°C) x TCARRIER where TCARRIER= carrier or heatsink temperature above 22°C (coefficient of de-rating formula is the Thermal Conductivity) Example: For a 55 °C carrier temperature: PTOT = 1.4 - (0.004 x (55 – 22)) = 1.26W 4Users should avoid exceeding 80% of 2 or more Limits simultaneously 5For optimum heatsinking eutectic die attach is recommended; conductive epoxy die attach is acceptable with some degradation in thermal de-rating performance (PTOT = 550mW) 6Thermal Resistivity: The nominal value of 250°C/W is stated for the input stage, which will reach temperature limits before the output stage. The aggregate MMIC thermal resistivity is approximately 80 °C/W. PAD LAYOUT: 2 Note: Co-ordinates are referenced from the bottom left hand corner of the die to the centre of bond pad opening PARAMETER SYMBOL TEST CONDITIONS ABSOLUTE MAXIMUM Supply Voltage VDD For any operating current 8V Supply Current IDD For VDD < 7V 75% IDSS RF Input Power PIN For standard bias conditions -8dBm Storage Temperature TSTG Non-Operating Storage -40°C to 150°C Total Power Dissipation 2,3 PTOT See De-Rating Note below 1400mW Gain Compression Comp. Under any bias conditions 5dB Simultaneous Combination of Limits 4 2 or more Max. Limits 80% PAD NAME DESCRIPTION PIN COORDINATES (µm) A IN RFIN 104, 836 B B ROUT 1962, 822 C VD Drain Voltage 770, 1522 D-F Stage 1: Source bias resistors 415/556/696,143 G-I Stage 2: Source bias resistors 821/962/1102,143 J-L Stage 3: Source bias resistors 1234/1374/1513, 143 DIE SIZE ( μm) DIE THICKNESS ( μm) MIN. BOND PAD PITCH ( μm) MIN. BOND PAD OPENING ( μm x μm ) 1624 x 2050 100 100 100 x 100 C A B D E F G H I J K L |
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