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ADC121S101CIMF Datasheet(PDF) 6 Page - National Semiconductor (TI) |
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ADC121S101CIMF Datasheet(HTML) 6 Page - National Semiconductor (TI) |
6 / 17 page ADC121S101 Timing Specifications (Continued) Note 3: When the input voltage at any pin exceeds the power supply (that is, VIN < GND or VIN > VA), the current at that pin should be limited to 10 mA. The 20 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 10 mA to two. The Absolute Maximum Rating specification does not apply to the VA pin. The current into the VA pin is limited by the Analog Supply Voltage specification. Note 4: The absolute maximum junction temperature (TJmax) for this device is 150˚C. The maximum allowable power dissipation is dictated by TJmax, the junction-to-ambient thermal resistance ( θJA), and the ambient temperature (TA), and can be calculated using the formula PDmax=(TJmax − TA)/ θJA. The values for maximum power dissipation listed above will be reached only when the device is operated in a severe fault condition (e.g. when input or output pins are driven beyond the power supply voltages, or the power supply polarity is reversed). Obviously, such conditions should always be avoided. Note 5: Human body model is 100 pF capacitor discharged through a 1.5 k Ω resistor. Machine model is 220 pF discharged through zero ohms. Note 6: Reflow temperature profiles are different for lead-free and non-lead-free packages. Note 7: Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level). Note 8: This is the frequency range over which the electrical performance is guaranteed. The device is functional over a wider range which is specified under Operating Ratings. Note 9: Data sheet min/max specification limits are guaranteed by design, test, or statistical analysis. Note 10: Minimum Quiet Time required by bus relinquish and the start of the next conversion. Note 11: Measured with the timing test circuit shown in Figure 1 and defined as the time taken by the output signal to cross 1.0V. Note 12: Measured with the timing test circuit shown in Figure 1 and defined as the time taken by the output signal to cross 1.0V or 2.0V. Note 13: tDIS is derived from the time taken by the outputs to change by 0.5V with the timing test circuit shown in Figure 1. The measured number is then adjusted to remove the effects of charging or discharging the output capacitance. This means that tDIS is the true bus relinquish time, independent of the bus loading. www.national.com 6 |
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