7

FN2810.9

April 25, 2007

AC Test Load Circuit

AC Electrical Specifications

PARAMETER

SYMBOL

NOTES

-33 (33MHz)

-40 (40MHz)

UNITS

MIN

MAX

MIN

MAX

Clock Period

30

-

25

-

ns

Clock High

12

-

10

-

ns

Clock Low

12

-

10

-

ns

SCLK High/Low

12

-

10

-

ns

Setup Time SD to SCLK Going High

12

-

12

-

ns

Hold Time SD from SCLK Going High

0-0-

ns

Setup Time SFTEN, MSB/LSB to SCLK Going High

15

-

12

-

ns

Hold Time SFTEN, MSB/LSB from SCLK Going High

0-0-

ns

Setup Time SCLK High to CLK Going High

Note 6

16

-

15

-

ns

Setup Time P0-1 to CLK Going High

15

-

12

-

ns

Hold Time P0-1 from CLK Going High

1-1-

ns

Setup Time LOAD, TXFR, ENPHAC, SEL_L/M

to CLK Going High

15

-

13

-

ns

Hold Time LOAD, TXFR, ENPHAC, SEL_L/M

from CLK Going High

1-1-

ns

CLK to Output Delay

215213

ns

Output Rise, Fall Time

Note 7

8

-

8

-

ns

NOTES:

5. AC testing is performed as follows: Input levels (CLK Input) 4.0V and 0V; Input levels (all other inputs) 0V and 3.0V; Timing reference levels

6. If TXFR is active, care must be taken to not violate setup and hold times as data from the shift registers may not have settled before CLK occurs.

7. Controlled via design or process parameters and not directly tested. Characterized upon initial design and after major process and/or design

changes.

EQUIVALENT CIRCUIT

1.5V

DUT

±

NOTE: Test head capacitance.

HSP45102