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CLC001AJE Datasheet(PDF) 6 Page - National Semiconductor (TI) |
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CLC001AJE Datasheet(HTML) 6 Page - National Semiconductor (TI) |
6 / 11 page Device Operation INPUT INTERFACING Numerous input configurations exist for applying PECL, LVPECL, and LVDS signals to the input of the CLC001. Inputs may be single-ended or differential, AC or DC coupled. The V BB pin may be used to provide a DC bias voltage to the inputs. Leave this pin as a no connect when no bias is needed. Note that DC-coupled inputs such as direct LVDS and LVPECL connections are self-biasing and do not require use of the V BB pin. IBB, the current produced by the VBB pin, depends on R REF. For a given RREF, the IBB current will remain constant, and the bias voltage is determined by the value of resistance, R BB, between the VBB pin and ground. Figure 3 and Figure 4 show how R BB corresponds to some common V BB values with RREF held at 1.91 k Ω and 1.5 kΩ, respectively. Some common input configurations are shown in Figure 5 through Figure 9. 10132911 FIGURE 3. R BB vs. VBB for RREF = 1.91 k Ω 10132912 FIGURE 4. R BB vs. VBB for RREF = 1.5 k Ω www.national.com 6 |
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