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ISL8484IU Datasheet(PDF) 7 Page - Intersil Corporation |
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ISL8484IU Datasheet(HTML) 7 Page - Intersil Corporation |
7 / 15 page 7 FN6128.3 June 14, 2007 FIGURE 2A. MEASUREMENT POINTS FIGURE 2B. TEST CIRCUIT FIGURE 2. CHARGE INJECTION FIGURE 3A. MEASUREMENT POINTS Repeat test for all switches. CL includes fixture and stray capacitance. FIGURE 3B. TEST CIRCUIT FIGURE 3. BREAK-BEFORE-MAKE TIME FIGURE 4. OFF ISOLATION TEST CIRCUIT FIGURE 5. rON TEST CIRCUIT Test Circuits and Waveforms (Continued) VOUT ΔVOUT ON OFF ON Q = ΔVOUT x CL SWITCH OUTPUT LOGIC INPUT V+ 0V CL VOUT RG VG GND COM NO OR NC V+ C LOGIC INPUT IN Repeat test for all switches. 90% V+ 0V tD LOGIC INPUT SWITCH OUTPUT 0V VOUT LOGIC INPUT IN COM RL CL VOUT 35pF 50 Ω NO NC V+ GND VNX C ANALYZER RL SIGNAL GENERATOR V+ C 0V OR V+ NO OR NC COM IN GND Signal direction through switch is reversed, worst case values are recorded. Repeat test for all switches. V+ C 0V OR V+ NO OR NC COM IN GND VNX V1 rON = V1/100mA 100mA Repeat test for all switches. ISL8484 |
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