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HSP50415 Datasheet(PDF) 10 Page - Intersil Corporation |
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HSP50415 Datasheet(HTML) 10 Page - Intersil Corporation |
10 / 29 page 10 FN4559.6 April 23, 2007 Iout<3:0>:Qout<3:0>. See Figure 7 for a constellation mapping example. For bit widths less than 4-bits the data in the RAM may simply be zero’s for the unused bit positions and the unused addresses since the HSP50415 will discard the unused bits. For example, if the user programs the number of bits to be 1 and the upper bits of the DIN<15:0> bus are tied to “0”, the user need only program addresses 0, 1, 16 and 17 since the other addresses will never be selected. In this example, the only data that is used will be memory address bits 4 and 0 since these map to I<0> and Q<0> respectively. For data bit widths larger than 4 bits or if mapping is not required, the constellation mapper may be bypassed. FIGURE 7. CONSTELLATION MAPPING MAP I Q 16 / “0x0008” 16 / “0x000A” 8 / “0x8A” Address 0x8A is formed from the lower 4-bits of I and Q data LOOK-UP I Q 16 / “0x0009” 16 / “0x000B” Address 0x8A is previously loaded with data 0x9B via the control bus 0x9B 0xFF 0x00 Address CONSTELLATION MAPPER DATA TO SHAPING FILTERS DATA FROM FIFO ADDRESS TABLE RAM Shaping FIR Filters Following the constellation mapping, the I/Q data pair is input to the programmable FIR filters for the first stage of interpolation. The interpolating FIR filters’ have programmable coefficients and must be loaded via the microprocessor interface. The I and Q filter stages are identical and may be loaded simultaneously or separately thus allowing for different gains and responses through the FIR filter if desired. The loading options are programmable including readback modes and will be discussed in detail in the ‘Microprocessor Interface’ section. Since the hardware for the I and Q filters is identical, further discussion will pertain to a single channel. The basic interpolation rates allowed through the FIR are x4, x8 or x16. An optional decimate by 2 mode is available that subsamples the output of the filter thus reducing the interpolation rate by a factor of 2. Each filter multiplication is implemented as a series of shifts and adds thus constraining the maximum input symbol rate as follows: symbolRateMax is the smaller of: (CLK * 2 * 2^twoBitMode) / (#bits * interpolationRate) and CLK/4 where CLK is the final sample rate clock (100MHz max), #bits is the data bit width of a single channel and twoBitMode is a special processing mode where 2-bits at a time are computed. The gain through the filter is: A = (sum of coefficients) / interpolation rate The FIR filter contains saturation logic in the event that the final output peaks over 1.0. Table 3 outlines the filter characteristics for the various interpolation rates. TABLE 3. FIR FILTER CHARACTERISTICS 2-BITMODE INTERP. RATE SYMBOL SPAN # FILTER TAPS 0 x4 24 96 0 x8 20 160 0 x16 16 256 1 x4 12 48 1 x8 10 80 1 x16 8 128 The programmable coefficients are stored in RAM as bit- sliced sums of products. The data exits the interpolating FIR filters as a parallel I<15:0> and Q<15:0> data stream at the interpolated sample rate. These filters may be totally bypassed if higher input symbol rates are required. When bypassed, the RAMs may be loaded with all zeros for power conservation. Post FIR Gain Control Following the FIR filter pair is a gain stage where I and Q are scaled equally. The programmable gain consists of a 6-bit mantissa and a 4-bit exponent stage. The equation for the gain is as follows: dataOut<15:0> = (dataIn<15:0> * 1.MMMMMM) * 2 ^ (EEEE - 11) where MMMMMM denotes the 6-bit gain value and EEEE is the 4-bit shift value. For a gain of 1.0 through this stage, program the mantissa to 0x00 and the exponent to 0xB. This stage is implemented with a signed 16-bit by unsigned 7-bit multiplier with the HSP50415 |
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