6

FN2919.9

April 26, 2007

Application Information

Static Protection

All devices are static protected by the use of input diodes.

However, strong static fields should be avoided, as it is

possible for the strong fields to cause degraded diode

junction characteristics, which may result in increased input

leakage currents.

Latchup Avoidance

Junction-isolated CMOS circuits employ configurations which

produce a parasitic 4-layer (PNPN) structure. The 4-layer

structure has characteristics similar to an SCR, and under

certain circumstances may be triggered into a low impedance

state resulting in excessive supply current. To avoid this

condition, no voltage greater than 0.3V beyond the supply

rails may be applied to any pin. In general, the op amp

supplies must be established simultaneously with, or before

any input signals are applied. If this is not possible, the drive

circuits must limit input current flow to 2mA to prevent latchup.

which allows the amplifier to be set to nominal quiescent

currents of 10

μA, 100μA or 1mA. These current settings

change only very slightly over the entire supply voltage

control terminal, permitting user selection of quiescent

voltage from V+ - 0.8 to V- +0.8 can be used.

NOTE: The output current available is a function of the quiescent

current setting. For maximum peak-to-peak output voltage swings

into low impedance loads, IQ of 1mA should be selected.

Output Stage and Load Driving Considerations

Each amplifiers’ quiescent current flows primarily in the

This allows output swings to almost the supply rails for

output loads of 1M

Ω, 100kΩ, and 10kΩ, using the output

stage in a highly linear class A mode. In this mode,

crossover distortion is avoided and the voltage gain is

maximized. However, the output stage can also be operated

in Class AB for higher output currents. (See graphs under

Typical Operating Characteristics). During the transition from

Class A to Class B operation, the output transfer

characteristic is non-linear and the voltage gain decreases.

Input Offset Nulling

Offset nulling may be achieved by connecting a 25k pot

between the BAL terminals with the wiper connected to V+.

At quiescent currents of 1mA and 100

μA the nulling range

Frequency Compensation

The ICL7611 and ICL7612 are internally compensated, and

are stable for closed loop gains as low as unity with

capacitive loads up to 100pF.

Extended Common Mode Input Range

The ICL7612 incorporates additional processing which

allows the input CMVR to exceed each power supply rail by

in the positive direction, but may exceed the negative supply

the input CMVR would be +0.6V to -1.1V).

A and B grades only.

Output swings to within a few millivolts of the supply rails are

applications where greater common mode range is

desirable, refer to the description of ICL7612 above.

Typical Applications

The user is cautioned that, due to extremely high input

impedances, care must be exercised in layout, construction,

board cleanliness, and supply filtering to avoid hum and

noise pickup.

chosen by the designer with regard to frequency response

and power dissipation.

ICL7612

+

-

FIGURE 1. SIMPLE FOLLOWER (NOTE 4)

ICL7612

+

-

100k

+5

+5

1M

TO CMOS OR

LPTTL LOGIC

NOTE:

4. By using the ICL7612 in this application, the circuit will follow rail

to rail inputs.

FIGURE 2. LEVEL DETECTOR (NOTE 4)

ICL7611, ICL7612