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X25256S8IG Datasheet(PDF) 5 Page - IC MICROSYSTEMS |
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X25256S8IG Datasheet(HTML) 5 Page - IC MICROSYSTEMS |
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5 / 17 page  X25256 – Preliminary Information Characteristics subject to change without notice. 5 of 17 www.icmic.com can be read sequentially by continuing to provide clock pulses. The address is automatically incremented to the next higher address after each byte of data is shifted out. When the highest address is reached ($7FFF) the address counter rolls over to address $0000 allowing the read cycle to be continued indefinitely. The read operation is terminated by taking CS HIGH. Refer to the read E 2PROM array operation sequence illustrated in Figure 2. To read the status register the CS line is first pulled LOW to select the device followed by the 8-bit RDSR instruction. After the RDSR opcode is sent, the contents of the status register are shifted out on the SO line. Figure 3 illustrates the read status register sequence. WP WPEN Memory Array Not Block Protected Memory Array Block Protected Block Lock Bits WPEN Bit Protection HIGH X Writable Blocked Writable Writable Software LOW 0 Writable Blocked Writable Writable Software LOW 1 Writable Blocked Writes Blocked Writes Blocked Hardware Write Sequence Prior to any attempt to write data into the X25256, the “write enable” latch must first be set by issuing the WREN instruction (See Figure 4). CS is first taken LOW, then the WREN instruction is clocked into the X25256. After all eight bits of the instruction are trans- mitted, CS must then be taken HIGH. If the user con- tinues the write operation without taking CS HIGH after issuing the WREN instruction, the write operation will be ignored. To write data to the E 2 PROM memory array, the user issues the WRITE instruction, followed by the address and then the data to be written. This is minimally a thirty- two clock operation. CS must go LOW and remain LOW for the duration of the operation. The host may continue to write up to 64 bytes of data to the X25256. The only restriction is the 64 bytes must reside on the same page. If the address counter reaches the end of the page and the clock continues, the counter will “roll over” to the first address of the page and overwrite any data that may have been written. For the write operation (byte or page write) to be com- pleted, CS can only be brought HIGH after bit 0 of data byte N is clocked in. If it is brought HIGH at any other time the write operation will not be completed. Refer to Figures 5 and 6 below for a detailed illustration of the write sequences and time frames in which CS going HIGH are valid. To write to the status register, the WRSR instruction is followed by the data to be written. Data bits 0, 1, 5, and 6 are “don’t care”. Figure 7 illustrates this sequence. While the write is in progress following a status register or E 2 PROM write sequence, the status register may be read to check the WIP bit. During this time the WIP bit will be HIGH. Hold Operation The HOLD input should be HIGH (at VIH ) under normal operation. If a data transfer is to be interrupted HOLD can be pulled LOW to suspend the transfer until it can be resumed. The only restriction is the SCK input must be LOW when HOLD is first pulled LOW and SCK must also be LOW when HOLD is released. The HOLD input may be tied HIGH either directly to V CC or tied to VCC through a resistor. Operational Notes The X25256 powers-up in the following state: – The device is in the low power standby state. – A HIGH to LOW transition on CS is required to enter an active state and receive an instruction. – SO pin is high impedance. – The “write enable” latch is reset. Data Protection The following circuitry has been included to prevent inadvertent writes: – The “write enable” latch is reset upon power-up. – A WREN instruction must be issued to set the “write enable” latch. – CS must come HIGH at the proper clock count in order to start a write cycle. |
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