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GE28F320C3TC70 Datasheet(HTML) 26 Page - Intel Corporation

Part No. GE28F320C3TC70
Description  Advanced Boot Block Flash Memory (C3)
Download  68 Pages
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Maker  INTEL [Intel Corporation]
Homepage  http://www.intel.com
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GE28F320C3TC70 Datasheet(HTML) 26 Page - Intel Corporation

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Intel£ Advanced+ Boot Block Flash Memory (C3)
26
Datasheet
10
Alt. Prog Set-Up
Operates the same as Program Set-up command. (See 0x40/Program Set-Up)
00
Invalid/
Reserved
Unassigned commands should not be used. Intel reserves the right to redefine these codes for
future functions.
NOTE:
See Appendix A, “Write State Machine States” for mode transition information.
Table 8.
Command Codes and Descriptions
Code
(HEX)
Device Mode
Command Description
Table 9.
Status Register Bit Definition
WSMS
ESS
ES
PS
VPPS
PSS
BLS
R
76543
210
NOTES:
SR[7] WRITE STATE MACHINE STATUS (WSMS)
1 = Ready
0= Busy
Check Write State Machine bit first to determine Word Program
or Block Erase completion, before checking program or erase-
status bits.
SR[6] = ERASE-SUSPEND STATUS (ESS)
1 = Erase Suspended
0= EraseIn Progress/Completed
When Erase Suspend is issued, WSM halts execution and sets
both WSMS and ESS bits to “1.” ESS bit remains set to “1” until
an Erase Resume command is issued.
SR[5] = ERASE STATUS (ES)
1= Error InBlock Erase
0 = Successful Block Erase
When this bit is set to “1,” WSM has applied the max. number
of erase pulses to the block and is still unable to verify
successful block erasure.
SR[4] = PROGRAM STATUS (PS)
1 = Error in Programming
0 = Successful Programming
When this bit is set to “1,” WSM has attempted but failed to
program a word/byte.
SR[3] = VPP STATUS (VPPS)
1= VPP Low Detect, Operation Abort
0= VPP OK
The VPP status bit does not provide continuous indication of
VPP level. The WSM interrogates VPP level only after the
Program or Erase command sequences have been entered,
and informs the system if VPP has not been switched on. The
VPP is also checked before the operation is verified by the
WSM. The VPP status bit is not guaranteed to report accurate
feedback between VPPLK and VPP1Min.
SR[2] = PROGRAM SUSPEND STATUS (PSS)
1 = Program Suspended
0 = Program in Progress/Completed
When Program Suspend is issued, WSM halts execution and
sets both WSMS and PSS bits to “1.” PSS bit remains set to “1”
until a Program Resume command is issued.
SR[1] = BLOCK LOCK STATUS
1= Prog/Erase attemptedonalockedblock; Operation
aborted.
0= No operationtolockedblocks
If a Program or Erase operation is attempted to one of the
locked blocks, this bit is set by the WSM. The operation
specifiedisabortedand thedeviceisreturnedtoreadstatus
mode.
SR[0] = RESERVED FOR FUTURE ENHANCEMENTS (R)
This bit is reserved for future use and should be masked out
when polling the status register.
NOTE:
A Command-Sequence Error is indicated when SR[4], SR[5], and SR[7] are set.


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