GE28F320C3BC70 datasheet(46/68 Pages) INTEL

Part #	GE28F320C3BC70

Description	Advanced Boot Block Flash Memory (C3)

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Intel£ Advanced+ Boot Block Flash Memory (C3)

46

Datasheet

Table 20. Write Operations—64Mbit Density

#Sym

Parameter

Density

64 Mbit

Unit

Product

80 ns

VCC

2.7V –3.6 V

Note

Min

W1

tPHWL /

tPHEL

RP# High Recovery to WE# (CE#) Going Low

4,5

150

ns

W2

tELWL /

tWLEL

CE# (WE#) Setup to WE# (CE#) Going Low

4,5

0

ns

W3

tWLWH /

tELEH

WE#(CE#) PulseWidth

1,4,5

60

ns

W4

tDVWH /

tDVEH

Data Setup to WE# (CE#) Going High

2,4,5

40

ns

W5

tAVWH /

tAVEH

Address Setup to WE# (CE#) Going High

2,4,5

60

ns

W6

tWHEH /

tEHWH

CE# (WE#) Hold Time from WE# (CE#) High

4,5

0

ns

W7

tWHDX /

tEHDX

Data Hold Time from WE# (CE#) High

2,4,5

0

ns

W8

tWHAX /

tEHAX

Address Hold Time from WE# (CE#) High

2,4,5

0

ns

W9

tWHWL /

tEHEL

WE#(CE#) PulseWidth High

1,4,5

30

ns

W10

tVPWH /

tVPEH

VPP Setup to WE# (CE#) Going High

3,4,5

200

ns

W11

tQVVL

VPP Hold from Valid SRD

3,4

0

ns

W12

tBHWH /

tBHEH

WP#Setup to WE#(CE#) GoingHigh

3,4

0

ns

W13

tQVBL

WP# Hold from Valid SRD

3,4

0

ns

W14

tWHGL

WE#HightoOE# GoingLow

3,4

30

ns

NOTES:

1. Write pulse width (tWP) is defined from CE# or WE# going low (whichever goes low last) to CE# or

WE# going high (whichever goes high first). Hence, tWP =tWLWH =tELEH =tWLEH =tELWH.

Similarly, write pulse width high (tWPH) is defined from CE# or WE# going high (whichever goes

high first) to CE# or WE# going low (whichever goes low last). Hence,

tWPH =tWHWL =tEHEL =tWHEL =tEHWL.

2. Refer to Table 7, “Command Bus Operations” on page 24 for valid AIN or DIN.

3. Sampled, but not 100% tested.

4. See Figure 11, “AC Input/Output Reference Waveform” on page 49 for timing measurements and

maximum allowable input slew rate.

5. See Figure 9, “Write Operations Waveform” on page 47.

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