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ISL55110_0712 Datasheet(PDF) 5 Page - Intersil Corporation |
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ISL55110_0712 Datasheet(HTML) 5 Page - Intersil Corporation |
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5 / 15 page  5 FN6228.2 December 12, 2007 ISL55110 INPUT INPUT RISE AND FALL TIMES ≤2ns CL 4.7µF 0.1µF + OUTPUT VH = 12V 10% 10% 90% tf 90% tr ≈0.4V 12V INPUT +3V 0V OUTPUT INX IN FIGURE 1. TEST CIRCUIT RISE (tR)/FALL(tF) THRESHOLDS ISL55110 INPUT INPUT RISE AND FALL TIMES ≤2ns CL 4.7µF 0.1µF + OUTPUT VH = 12V 50% 50% 50% 50% tpdR tpdF ≈0.4V 12V INPUT +3V 0V OUTPUT OA AND OB ISLS55110 IN-X IN OUTPUT OA ISLS55111 50% 50% 12V 0V OUTPUT OB ISLS55111 tSKEWR = tpdR CHN1 - tpdR CHN2 FIGURE 2. TEST CIRCUIT PROPAGATION TPD DELAY ISL55110, ISL55111 |
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