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DS1689S+R Datasheet(PDF) 2 Page - Dallas Semiconductor |
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DS1689S+R Datasheet(HTML) 2 Page - Dallas Semiconductor |
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2 / 36 page  DS1689/DS1693 2 of 36 PIN DESCRIPTION PIN SO EDIP NAME FUNCTION 1 1 VBAUX Auxiliary Battery Supply. Auxiliary battery input required for kickstart and wake-up features. This input also supports clock/calendar and External NV RAM if VBAT is at lower voltage or is not present. A standard +3V lithium cell or other energy source can be used. Battery voltage must be held between +2.5V and +3.7V for proper operation. If VBAUX is not going to be used it should be grounded and auxiliary battery enable bit bank 1, register 4BH, should = 0. 2, 3 — X1, X2 Connections for Standard 32.768kHz Quartz Crystal. For greatest accuracy, the DS1689 must be used with a crystal that has a specified load capacitance of either 6pF or 12.5pF. The crystal select (CS) bit in Extended Control Register 4B is used to select operation with a 6pF or 12.5pF crystal. The crystal is attached directly to the X1 and X2 pins. There is no need for external capacitors or resistors. Note: X1 and X2 are very high-impedance nodes. It is recommended that they and the crystal by guard-ringed with ground and that high- frequency signals be kept away from the crystal area. For more information on crystal selection and crystal layout considerations, refer to Application Note 58: Crystal Considerations with Dallas Real Time Clocks. The DS1689 can also be driven by an external 32.768kHz oscillator. In this configuration, the X1 pin is connected to the external oscillator signal and the X2 pin is floated. 4 4 RCLR Active-Low RAM Clear Input. If enabled by software, taking RCLR low will result in the clearing of the 114 bytes of user RAM. When enabled, RCLR can be activated whether or not VCC is present. 5–12 5–12 AD0–AD7 Multiplexed Address/Data Bus. Multiplexed buses save pins because address information and data information time-share the same signal paths. The addresses are present during the first portion of the bus cycle and the same pins and signal paths are used for data in the second portion of the cycle. Address/data multiplexing does not slow the access time of the DS1689 since the bus change from address to data occurs during the internal RAM access time. Addresses must be valid prior to the latter portion of ALE, at which time the DS1689/DS1693 latches the address. Valid write data must be present and held stable during the latter portion of the WR pulse. In a read cycle, the DS1689/ DS1693 outputs 8 bits of data during the latter portion of the RD pulse. The read cycle is terminated and the bus returns to a high impedance state as RD transitions high. The address/data bus also serves as a bidirectional data path for the external extended RAM. |
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