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AD9879 Datasheet(PDF) 11 Page - Analog Devices |
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AD9879 Datasheet(HTML) 11 Page - Analog Devices |
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11 / 32 page  AD9879 Rev. A | Page 11 of 32 THEORY OF OPERATION To gain a general understanding of the AD9879, refer to the block diagram of the device architecture in Figure 3. The device consists of a transmit path, receive path, and auxiliary functions, such as a DPLL, a Σ-Δ DAC, a serial control port, and a cable amplifier interface. TRANSMIT PATH The transmit path contains an interpolation filter, a complete quadrature digital upconverter, an inverse sinc filter, and a 12-bit current output DAC. The maximum output current of the DAC is set by an external resistor. The Tx output PGA provides additional transmit signal level control. The transmit path interpolation filter provides an upsampling factor of 16 with an output signal bandwidth as high as 5.8 MHz. Carrier frequencies up to 65 MHz with 26 bits of frequency tuning resolution can be generated by the direct digital synthesizer (DDS). The transmit DAC resolution is 12 bits and can run at sampling rates as high as 232 MSPS. Analog output scaling from 0.0 dB to 7.5 dB in 0.5 dB steps is available to preserve SNR when reduced output levels are required. DATA ASSEMBLER The AD9879 data path operates on two 12-bit words, the I and Q components, which compose a complex symbol. The data assembler builds the 24-bit complex symbols from four consecutive 6-bit nibbles read over the TxIQ[5:0] bus. The nibbles are strobed synchronous to the master clock, MCLK, into the data assembler. A high level on TxSYNC signals the start of a transmit symbol. The first two nibbles of the symbol form the I component, and the second two nibbles form the Q component. Symbol components are assumed to be in twos complement format. The timing of the interface is fully described in the Transmit Timing section of this data sheet. TXIQ TXSYNC MCLK REFCLK CA_PORT PROFILE SPORT RXIQ[3:0] RXSYNC IF[11:0] FSADJ XTAL OSCIN Σ-∆_OUT FLAG1 I INPUT Q INPUT IF10 INPUT IF12 INPUT VIDEO INPUT 6 3 12 12 10 7 12 AD9879 DATA ASSEMBLER QUADRATURE MODULATOR FIR LPF CIC LPF COS SIN (fIQCLK) (fSYSCLK) (fOSCIN) (fMCLK) DAC GAIN CONTROL PLL OSCIN × M DDS MUX MUX CA INTERFACE PROFILE SELECT SERIAL INTERFACE 12 4 ÷4 SINC–1 MUX DAC IQ IF CLAMP LEVEL ADC ADC ADC ADC MUX DAC ÷2 ÷8 ÷4 ÷2 12 12 (fOSCIN) (fOSCIN) 7 ÷R 4 4 12 I Q RXPORT TX Σ-∆ INPUT REGISTER – + — ÷2 4 4 4 12 SINC–1 BYPASS Σ-∆ Figure 3. Block Diagram |
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