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ADSP-2189MBST-266 Datasheet(PDF) 6 Page - Analog Devices |
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ADSP-2189MBST-266 Datasheet(HTML) 6 Page - Analog Devices |
6 / 32 page REV. 0 ADSP-2189M –6– faster rate than can be serviced, due to the additional time the processor takes to come out of the idle state (a maximum of n processor cycles). SYSTEM INTERFACE Figure 2 shows typical basic system configurations with the ADSP-2189M, two serial devices, a byte-wide EPROM and optional external program and data overlay memories (mode selectable). Programmable Wait-State generation allows the processor connects easily to slow peripheral devices. The ADSP-2189M also provides four external interrupts and two serial ports or six external interrupts and one serial port. Host Memory Mode allows access to the full external data bus, but limits addressing to a single address bit (A0). Additional system peripherals can be added in this mode through the use of exter- nal hardware to generate and latch address signals. 1/2x CLOCK OR CRYSTAL SERIAL DEVICE SERIAL DEVICE SCLK1 RFS1 OR IRQ0 TFS1 OR IRQ1 DT1 OR FO DR1 OR FI SPORT1 SCLK0 RFS0 TFS0 DT0 DR0 SPORT0 A0-A21 DATA CS BYTE MEMORY I/O SPACE (PERIPHERALS) CS DATA ADDR DATA ADDR 2048 LOCATIONS OVERLAY MEMORY TWO 8K PM SEGMENTS TWO 8K DM SEGMENTS D23-0 A13-0 D23-8 A10-0 D15-8 D23-16 A13-0 14 24 FL0-2 CLKIN XTAL ADDR13-0 DATA23-0 BMS IOMS PMS DMS CMS BR BG BGH PWD ADSP-2189M IRQ2/PF7 IRQE/PF4 IRQL0/PF5 IRQL1/PF6 MODE C/PF2 MODE B/PF1 MODE A/PF0 FULL MEMORY MODE PWDACK WR RD MODE D/PF3 1/2x CLOCK OR CRYSTAL SERIAL DEVICE SERIAL DEVICE SYSTEM INTERFACE OR CONTROLLER 16 1 16 SCLK1 RFS1 OR IRQ0 TFS1 OR IRQ1 DT1 OR FO DR1 OR FI SPORT1 SCLK0 RFS0 TFS0 DT0 DR0 SPORT0 IRD/D6 IWR/D7 IS/D4 IAL/D5 IACK/D3 IAD15-0 IDMA PORT FL0-2 CLKIN XTAL A0 DATA23-8 BMS IOMS PMS DMS CMS BR BG BGH PWD ADSP-2189M IRQ2/PF7 IRQE/PF4 IRQL0/PF5 IRQL1/PF6 MODE C/PF2 MODE B/PF1 MODE A/PF0 HOST MEMORY MODE PWDACK WR RD MODE D/PF3 Figure 2. ADSP-2189M Basic System Interface Clock Signals The ADSP-2189M can be clocked by either a crystal or a TTL- compatible clock signal. The CLKIN input cannot be halted, changed during operation, or operated below the specified frequency during normal opera- tion. The only exception is while the processor is in the power- down state. For additional information, refer to Chapter 9, ADSP-2100 Family User’s Manual, Third Edition for detailed information on this power-down feature. If an external clock is used, it should be a TTL-compatible signal running at half the instruction rate. The signal is con- nected to the processor’s CLKIN input. When an external clock is used, the XTAL input must be left unconnected. The ADSP-2189M uses an input clock with a frequency equal to half the instruction rate; a 37.50 MHz input clock yields a 15 ns processor cycle (which is equivalent to 77 MHz). Nor- mally, instructions are executed in a single processor cycle. All device timing is relative to the internal instruction clock rate, which is indicated by the CLKOUT signal when enabled. Because the ADSP-2189M includes an on-chip oscillator cir- cuit, an external crystal may be used. The crystal should be connected across the CLKIN and XTAL pins, with two capaci- tors connected as shown in Figure 3. Capacitor values are de- pendent on crystal type and should be specified by the crystal manufacturer. A parallel-resonant, fundamental frequency, microprocessor-grade crystal should be used. A clock output (CLKOUT) signal is generated by the processor at the processor’s cycle rate. This can be enabled and disabled by the CLKODIS bit in the SPORT0 Autobuffer Control Register. CLKIN CLKOUT XTAL DSP Figure 3. External Crystal Connections Reset The RESET signal initiates a master reset of the ADSP-2189M. The RESET signal must be asserted during the power-up se- quence to assure proper initialization. RESET during initial power-up must be held long enough to allow the internal clock to stabilize. If RESET is activated any time after power-up, the clock continues to run and does not require stabilization time. The power-up sequence is defined as the total time required for the crystal oscillator circuit to stabilize after a valid VDD is ap- plied to the processor and for the internal phase-locked loop (PLL) to lock onto the specific crystal frequency. A minimum of 2000 CLKIN cycles ensures that the PLL has locked but does not include the crystal oscillator start-up time. During this power-up sequence the RESET signal should be held low. On any subsequent resets, the RESET signal must meet the mini- mum pulsewidth specification, tRSP. The RESET input contains some hysteresis; however, if you use an RC circuit to generate your RESET signal, the use of an external Schmidt trigger is recommended. |
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