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FT232BM Datasheet(PDF) 3 Page - Future Technology Devices International Ltd. |
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FT232BM Datasheet(HTML) 3 Page - Future Technology Devices International Ltd. |
3 / 54 page DS2232C Version 1.2 © Future Technology Devices International Ltd. 2004 Page 3 of 54 FT2232C Dual USB UART / FIFO I.C. • Two Individually Configurable IO Channels Each of the FT2232C’s Channels (A and B) can be individually configured as a FT232BM-style UART interface, or as a FT245BM-style FIFO interface. In addition these channel can be configured in a number of special IO modes. • Integrated Power-On-Reset (POR) circuit The device incorporates an internal POR function. A RESET# pin is available to allow external logic to reset the device where required, however for most applications this pin can simply be hardwired to Vcc. A RSTOUT# pin is provided in order to allow the new POR circuit to provide a stable reset to external MCU and other devices. • Integrated RCCLK circuit Used to ensure that the oscillator and clock multiplier PLL frequency are stable prior to USB enumeration. • Integrated level converter on UART / FIFO interface and control signals Each channel of the FT2232C has its own independent VCCIO pin that can be supplied by between 3V to 5V. This allows each channel’s output voltage drive level to be individually configured. Thus allowing, for example 3.3V logic to be interfaced to the device without the need for external level converter I.C.’s. • Improved power management control for high- power USB Bus Powered devices The PWREN# pin will become active when the device is enumerated by USB, and be deactivated when the device is in USB suspend. This can be used to directly drive a transistor or P-Channel MOSFET in applications where power switching of external circuitry is required. The BM pull down enable feature (configured in the external EEPROM) is also retained. This will make the device gently pull down on the FIFO / UART IO lines when the power is shut off (PWREN# is high). In this mode any residual voltage on external circuitry is bled to GND when power is removed, thus ensuring that external circuitry controlled by PWREN# resets reliably when power is restored. • Support for Isochronous USB Transfers Whilst USB Bulk transfer is usually the best choice for data transfer, the scheduling time of the data is not guaranteed. For applications where scheduling latency takes priority over data integrity such as transferring audio and low bandwidth video data, the FT2232C offers the option of USB Isochronous transfer via configuration of bit in the EEPROM. • Send Immediate / Wake Up Signal Pin on each channel There is a Send Immediate / Wake Up (SI/WU) signal pins on each of the chips channels. These combine two functions on one pin. If USB is in suspend mode (and remote wakeup is enabled in the EEPROM), strobing this pin low will cause the device to request a resume from suspend (WakeUp) on the USB Bus. Normally, this can be used to wake up the Host PC. During normal operation, if this pin is strobed low any data in the device RX buffer will be sent out over USB on the next Bulk-IN request from the drivers regardless of the packet size. This can be used to optimise USB transfer speed for some applications. • Low suspend current The suspend current of the FT2232C is typically under 100 μA (excluding the 1.5K pull up resistor on USBDP) in USB suspend mode. This allows greater margin for peripherals to meet the USB Suspend current limit of 500uA. The FT2232C incorporates all of the enhancements introduced for the second generation FT232BM and FT245BM chips. These are summarised as follows :- 2.0 Features and Enhancements |
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Similar Description - FT232BM |
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