CY25701
Document Number: 001-07313 Rev. *B
Page 4 of 8
Note
2. Guaranteed by characterization, not fully tested.
3. Jitter is configuration dependent. Actual jitter depends upon output frequencies, spread percentage, temperature, and output load. For more information, see
the application note, “Jitter in PLL Based Systems: Causes, Effects, and Solutions” available at http://www.cypress.com/clock/appnotes.html or contact your
local Cypress Field Application Engineer.
AC Electrical Characteristics[2]
Parameter
Description
Condition
Min
Typ
Max
Unit
DC
Output Duty Cycle
SSCLK, Measured at VDD/2
45
50
55
%
tR
Output Rise Time
20%–80% of VDD, CL = 15 pF
–
–
2.7
ns
tF
Output Fall Time
20%–80% of VDD, CL = 15 pF
–
–
2.7
ns
TCCJ1
[3]
Cycle-to-Cycle Jitter SSCLK (Pin 3) SSCLK
≥133 MHz, Measured at V
DD/2
–
85
200
ps
25 MHz
≤ SSCLK <133 MHz, Measured at
VDD/2
–215
400
ps
SSCLK < 25 MHz, Measured at VDD/2
–
–
1% of
1/SSCK
s
TOE1
Output Disable Time (pin1 = OE)
Time from falling edge on OE to stopped
outputs (Asynchronous)
–150
350
ns
TOE2
Output Enable Time (pin1 = OE)
Time from rising edge on OE to outputs at a
valid frequency (Asynchronous)
–150
350
ns
TLOCK
PLL Lock Time
Time for SSCLK to reach valid frequency
–
–
10
ms
Application Circuit
Figure 1. Application Circuit Diagram
0.1 µF
VDD
1
2
3
4
OE
VSS
SSCLK
VDD
Power
CY25701