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ADSP-BF538 Datasheet(PDF) 8 Page - Analog Devices |
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ADSP-BF538 Datasheet(HTML) 8 Page - Analog Devices |
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8 / 56 page  Rev. 0 | Page 8 of 56 | May 2007 ADSP-BF538/ADSP-BF538F System Interrupt Controllers (SIC) The system interrupt controllers (SIC0, SIC1) provide the map- ping and routing of events from the many peripheral interrupt sources to the prioritized general-purpose interrupt inputs of the CEC. Although the ADSP-BF538/ADSP-BF538F processors provide a default mapping, the user can alter the mappings and priorities of interrupt events by writing the appropriate values into the interrupt assignment registers (SIC_IARx). Table 3 describes the inputs into the SICs and the default map- pings into the CEC. Event Control The ADSP-BF538/ADSP-BF538F processors provide the user with a very flexible mechanism to control the processing of events. In the CEC, three registers are used to coordinate and control events. Each register is 32 bits wide: • CEC interrupt latch register (ILAT) – The ILAT register indicates when events have been latched. The appropriate bit is set when the processor has latched the event and cleared when the event has been accepted into the system. This register is updated automatically by the controller, but it may also be written to clear (cancel) latched events. This register may be read while in supervisor mode and may only be written while in supervisor mode when the corre- sponding IMASK bit is cleared. • CEC interrupt mask register (IMASK) – The IMASK regis- ter controls the masking and unmasking of individual events. When a bit is set in the IMASK register, that event is unmasked and will be processed by the CEC when asserted. A cleared bit in the IMASK register masks the event, pre- venting the processor from servicing the event even though the event may be latched in the ILAT register. This register may be read or written while in supervisor mode. (Note that general-purpose interrupts can be globally enabled and disabled with the STI and CLI instructions, respectively.) • CEC interrupt pending register (IPEND) – The IPEND register keeps track of all nested events. A set bit in the IPEND register indicates the event is currently active or nested at some level. This register is updated automatically by the controller but may be read while in supervisor mode. Each SIC allows further control of event processing by provid- ing three 32-bit interrupt control and status registers. Each register contains a bit corresponding to each of the peripheral interrupt events shown in Table 3 on Page 8. Table 3. System and Core Event Mapping Event Source Core Event Name PLL Wakeup Interrupt IVG7 DMA Controller 0 Error IVG7 DMA Controller 1 Error IVG7 PPI Error Interrupt IVG7 SPORT0 Error Interrupt IVG7 SPORT1 Error Interrupt IVG7 SPORT2 Error Interrupt IVG7 SPORT3 Error Interrupt IVG7 SPI0 Error Interrupt IVG7 SPI1 Error Interrupt IVG7 SPI2 Error Interrupt IVG7 UART0 Error Interrupt IVG7 UART1 Error Interrupt IVG7 UART2 Error Interrupt IVG7 CAN Error Interrupt IVG7 Real Time Clock Interrupts IVG8 DMA0 Interrupt (PPI) IVG8 DMA1 Interrupt (SPORT0 Rx) IVG9 DMA2 Interrupt (SPORT0 Tx) IVG9 DMA3 Interrupt (SPORT1 Rx) IVG9 DMA4 Interrupt (SPORT1 Tx) IVG9 DMA8 Interrupt (SPORT2 Rx) IVG9 DMA9 Interrupt (SPORT2 Tx) IVG9 DMA10 Interrupt (SPORT3 Rx) IVG9 DMA11 Interrupt (SPORT3 Tx) IVG9 DMA5 Interrupt (SPI0) IVG10 DMA14 Interrupt (SPI1) IVG10 DMA15 Interrupt (SPI2) IVG10 DMA6 Interrupt (UART0 Rx) IVG10 DMA7 Interrupt (UART0 Tx) IVG10 DMA16 Interrupt (UART1 Rx) IVG10 DMA17 Interrupt (UART1 Tx) IVG10 DMA18 Interrupt (UART2 Rx) IVG10 DMA19 Interrupt (UART2 Tx) IVG10 Timer0, Timer1, Timer2 Interrupts IVG11 TWI0 Interrupt IVG11 TWI1 Interrupt IVG11 CAN Receive Interrupt IVG11 CAN Transmit Interrupt IVG11 Port F GPIO Interrupts A and B IVG12 MDMA0 Stream 0 Interrupt IVG13 MDMA0 Stream 1 Interrupt IVG13 MDMA1 Stream 0 Interrupt IVG13 MDMA1 Stream 1 Interrupt IVG13 Software Watchdog Timer IVG13 Table 3. System and Core Event Mapping (Continued) Event Source Core Event Name |
Similar Part No. - ADSP-BF538_07 |
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Similar Description - ADSP-BF538_07 |
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