 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
ADSP-BF538F Datasheet(PDF) 10 Page - Analog Devices |
|
||||||||||||||||||||||||||||||
ADSP-BF538F Datasheet(HTML) 10 Page - Analog Devices |
|
|
10 / 56 page  Rev. 0 | Page 10 of 56 | May 2007 ADSP-BF538/ADSP-BF538F WATCHDOG TIMER The ADSP-BF538/ADSP-BF538F processors include a 32-bit timer that can be used to implement a software watchdog func- tion. A software watchdog can improve system availability by forcing the processor to a known state through generation of a hardware reset, nonmaskable interrupt (NMI), or general-pur- pose interrupt, if the timer expires before being reset by software. The programmer initializes the count value of the timer, enables the appropriate interrupt, then enables the timer. Thereafter, the software must reload the counter before it counts to zero from the programmed value. This protects the system from remaining in an unknown state where software, which would normally reset the timer, has stopped running due to an external noise condition or software error. If configured to generate a hardware reset, the watchdog timer resets both the core and the processor peripherals. After a reset, software can determine if the watchdog was the source of the hardware reset by interrogating a status bit in the watchdog timer control register. The timer is clocked by the system clock (SCLK), at a maximum frequency of fSCLK. TIMERS There are four general-purpose programmable timer units in the ADSP-BF538/ADSP-BF538F processors. Three timers have an external pin that can be configured either as a pulse width modulator (PWM) or timer output, as an input to clock the timer, or as a mechanism for measuring pulse widths and peri- ods of external events. These timers can be synchronized to an external clock input to the PF1 pin (TACLK), an external clock input to the PPI_CLK pin (TMRCLK), or to the internal SCLK. The timer units can be used in conjunction with UART0 to measure the width of the pulses in the data stream to provide an auto-baud detect function for a serial channel. The timers can generate interrupts to the processor core provid- ing periodic events for synchronization, either to the system clock or to a count of external signals. In addition to the three general-purpose programmable timers, a fourth timer is also provided. This extra timer is clocked by the internal processor clock and is typically used as a system tick clock for generation of operating system periodic interrupts. SERIAL PORTS (SPORTs) The ADSP-BF538/ADSP-BF538F processors incorporate four dual-channel synchronous serial ports for serial and multipro- cessor communications. The SPORTs support the following features: •I2S capable operation. • Bidirectional operation – Each SPORT has two sets of inde- pendent transmit and receive pins, enabling 16 channels of I2S stereo audio. • Buffered (8-deep) transmit and receive ports – Each port has a data register for transferring data words to and from other processor components and shift registers for shifting data in and out of the data registers. • Clocking – Each transmit and receive port can either use an external serial clock or generate its own, in frequencies ranging from (fSCLK/131,070) Hz to (fSCLK/2) Hz. • Word length – Each SPORT supports serial data words from 3 bits to 32 bits in length, transferred most significant bit first or least significant bit first. • Framing – Each transmit and receive port can run with or without frame sync signals for each data word. Frame sync signals can be generated internally or externally, active high or low, and with either of two pulse widths and early or late frame sync. • Companding in hardware – Each SPORT can perform A-law or μ-law companding according to ITU recommen- dation G.711. Companding can be selected on the transmit and/or receive channel of the SPORT without additional latencies. • DMA operations with single-cycle overhead – Each SPORT can automatically receive and transmit multiple buffers of memory data. The processor can link or chain sequences of DMA transfers between a SPORT and memory. • Interrupts – Each transmit and receive port generates an interrupt upon completing the transfer of a data word or after transferring an entire data buffer or buffers through DMA. • Multichannel capability – Each SPORT supports 128 chan- nels out of a 1024 channel window and is compatible with the H.100, H.110, MVIP-90, and HMVIP standards. SERIAL PERIPHERAL INTERFACE (SPI) PORTS The ADSP-BF538/ADSP-BF538F processors incorporate three SPI compatible ports that enable the processor to communicate with multiple SPI compatible devices. The SPI interface uses three pins for transferring data: two data pins (master output-slave input, MOSIx, and master input-slave output, MISOx) and a clock pin (serial clock, SCKx). An SPI chip select input pin (SPIxSS) lets other SPI devices select the Figure 5. External Components for RTC RTXO C1 C2 X1 SUGGESTED COMPONENTS: ECLIPTEK EC38J (THROUGH-HOLE PACKAGE) EPSON MC405 12 pF LOAD (SURFACE MOUNT PACKAGE) C1 = 22 pF C2 = 22 pF R1 = 10M OHM NOTE: C1 AND C2 ARE SPECIFIC TO CRYSTAL SPECIFIED FOR X1. CONTACT CRYSTAL MANUFACTURER FOR DETAILS. C1 AND C2 SPECIFICATIONS ASSUME BOARD TRACE CAPACITANCE OF 3 pF. RTXI R1 |
Similar Part No. - ADSP-BF538F |
|
Similar Description - ADSP-BF538F |
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.NET |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
