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TLK1211RCP Datasheet(PDF) 3 Page - Texas Instruments |
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TLK1211RCP Datasheet(HTML) 3 Page - Texas Instruments |
3 / 20 page www.ti.com BLOCK DIAGRAM 2:1 MUX PRBS Generator 10 Bit Registers TD(0-9) PRBSEN LOOPEN Parallel to Serial Phase Generator Clock REFCLK Control Logic MODESEL ENABLE TESTEN Interpolator and Clock Extraction PRBS Verification Serial to Parallel and Comma Detect Clock RBC1 RBC0 SYNC/PASS RD(0-9) SYNCEN RBCMODE JTAG Control Register JTMS JTRSTN JTDI TCK JTDO 2:1 MUX 2:1 MUX Clock Data TXP TXN RXP RXN LOS TLK1211RCP ETHERNET TRANSCEIVERS SLLS658C – SEPTEMBER 2006 – REVISED SEPTEMBER 2007 Terminal Functions TERMINAL I/O DESCRIPTION NAME NO. SIGNAL MODESEL 15 I Mode select. This terminal selects between the 10-bit interface and a reduced 5-bit DDR P/D(1) interface. When low, the 10-bit interface (TBI) is selected. When pulled high, the 5-bit DDR mode is selected. The default mode is the TBI. LOS 26 O Loss of signal. Indicates a loss of signal on the high-speed differential inputs RXP and RXN. If the magnitude of RXP-RXN > 150 mV, then LOS = 1 which is a valid input signal. If the magnitude of RXP-RXN > 50 mV and < 150 mV, then LOS is undefined. If the magnitude of RXP-RXN < 50 mV, then LOS = 0 which is a loss of signal. RBCMODE 32 I Receive clock mode select. When RBCMODE and MODESEL are low, half-rate clocks are output P/D(1) on RBC0 and RBC1. When MODESEL is low and RBCMODE is high, a full baud-rate clock is output on RBC0 and RBC1 is held low. When MODESEL is high, RBCMODE is ignored and a full baud-rate clock is output on RBC0 and RBC1 is held low. RBC0 31 O Receive byte clock. RBC0 and RBC1 are recovered clocks used for synchronizing the 10-bit RBC1 30 output data on RD0–RD9. The operation of these clocks is dependent upon the receive clock mode selected. In the half-rate mode, the 10-bit output data words are valid on the rising edges of RBC0 and RBC1. These clocks are adjusted to half-word boundaries in conjunction with synchronous detect. The clocks are always expanded during data realignment and never slivered or truncated. RBC0 registers bytes 1 and 3 of received data. RBC1 registers bytes 0 and 2 of received data. In the normal rate mode, only RBC0 is valid and operates at 1/10th the serial data rate. Data is aligned to the rising edge. In the DDR mode, only RBC0 is valid and operates at 1/10th the serial data rate. Data is aligned on both the rising and falling edges. (1) P/D = Internal pulldown Copyright © 2006–2007, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Link(s): TLK1211RCP |
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