Figure 15-12. Master Burst SEND after Burst RECEIVE ........................................................................ 385
Figure 15-13. Slave Command Sequence ............................................................................................ 386
Figure 16-1.
CAN Module Block Diagram ........................................................................................... 411
Figure 16-2.
CAN Bit Time ................................................................................................................ 418
Figure 17-1.
Ethernet Controller Block Diagram .................................................................................. 452
Figure 17-2.
Ethernet Controller ......................................................................................................... 452
Figure 17-3.
Ethernet Frame ............................................................................................................. 454
Figure 18-1.
Analog Comparator Module Block Diagram ..................................................................... 496
Figure 18-2.
Structure of Comparator Unit .......................................................................................... 497
Figure 18-3.
Comparator Internal Reference Structure ........................................................................ 498
Figure 19-1.
PWM Module Block Diagram .......................................................................................... 507
Figure 19-2.
PWM Count-Down Mode ................................................................................................ 508
Figure 19-3.
PWM Count-Up/Down Mode .......................................................................................... 509
Figure 19-4.
PWM Generation Example In Count-Up/Down Mode ....................................................... 509
Figure 19-5.
PWM Dead-Band Generator ........................................................................................... 510
Figure 20-1.
QEI Block Diagram ........................................................................................................ 544
Figure 20-2.
Quadrature Encoder and Velocity Predivider Operation .................................................... 545
Figure 21-1.
Pin Connection Diagram ................................................................................................ 560
Figure 24-1.
Load Conditions ............................................................................................................ 579
Figure 24-2.
I
2C Timing ..................................................................................................................... 582
Figure 24-3.
External XTLP Oscillator Characteristics ......................................................................... 584
Figure 24-4.
Hibernation Module Timing ............................................................................................. 585
Figure 24-5.
SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing Measurement .............. 586
Figure 24-6.
SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer ............................. 586
Figure 24-7.
SSI Timing for SPI Frame Format (FRF=00), with SPH=1 ................................................. 587
Figure 24-8.
JTAG Test Clock Input Timing ......................................................................................... 588
Figure 24-9.
JTAG Test Access Port (TAP) Timing .............................................................................. 588
Figure 24-10. JTAG TRST Timing ........................................................................................................ 588
Figure 24-11. External Reset Timing (RST) .......................................................................................... 589
Figure 24-12. Power-On Reset Timing ................................................................................................. 590
Figure 24-13. Brown-Out Reset Timing ................................................................................................ 590
Figure 24-14. Software Reset Timing ................................................................................................... 590
Figure 24-15. Watchdog Reset Timing ................................................................................................. 590
Figure 25-1.
100-Pin LQFP Package .................................................................................................. 591
September 02, 2007
10
Preliminary
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