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TAS5706 Datasheet(PDF) 7 Page - Texas Instruments |
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TAS5706 Datasheet(HTML) 7 Page - Texas Instruments |
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7 / 62 page  www.ti.com TAS5706 SLOS550A – DECEMBER 2007 – REVISED DECEMBER 2007 TERMINAL FUNCTIONS (continued) TERMINAL TYPE 5-V TERMINATION DESCRIPTION (1) TOLERANT (2) NAME NO. BST_A 59 P High-side bootstrap supply for half-bridge A BST_B 61 P High-side bootstrap supply for half-bridge B BST_C 53 P High-side bootstrap supply for half-bridge C BST_D 55 P High-side bootstrap supply for half-bridge D BYPASS 56 O Nominally equal to VCC/8. Internal reference voltage for analog cells DVDD 15, P 3.3-V digital power supply 33 DVSS 20, P Digital ground 26 HPL_PWM 37 DO Headphone left-channel PWM output. HPR_PWM 38 DO Headphone right-channel PWM output. HPSEL 30 DI 5-V Headphone select, active high. When a logic HIGH is applied, device enters headphone mode and speakers are HARD MUTED. When a logic LOW is applied, device is in speaker mode and headphone outputs become line outputs or are disabled. LRCLK 22 DI 5-V Input serial audio data left/right clock (sampling rate clock) MCLK 34 DI 5-V MCLK is the clock master input. The input frequency of this clock can range from 4.9 MHz to 49 MHz. MUTE 21 DI 5-V Pullup Performs a soft mute of outputs, active-low. A logic low on this terminal sets the outputs equal to 50% duty cycle. A logic high on this terminal allows normal operation. The mute control provides a noiseless volume ramp to silence. Releasing mute provides a noiseless ramp to previous volume. OSC_RES 19 AO Oscillator trim resistor. Connect an 18.2-k Ω resistor to GND. OUT_A 4, 5 O Output, half-bridge A OUT_B 1, 64 O Output, half-bridge B OUT_C 49, O Output, half-bridge C 50 OUT_D 45, O Output, half-bridge D 46 PDN 17 DI 5-V Pullup Power down, active-low. PDN powers down all logic, stops all clocks, and outputs stops switching. When PDN is released, the device powers up all logic, starts all clocks, and performs a soft start that returns to the previous configuration determined by register settings. PGND_A 6, 7 P Power ground for half-bridge A PGND_B 2, 3 P Power ground for half-bridge B PGND_C 47, P Power ground for half-bridge C 48 PGND_D 43, P Power ground for half-bridge D 44 PLL_FLTM 12 AO PLL negative input PLL_FLTP 13 AI PLL positive input PVCC_A 8, 9 P Power supply input for half-bridge output A PVCC_B 62, P Power supply input for half-bridge output B 63 PVCC_C 51, P Power supply input for half-bridge output C 52 PVCC_D 41, P Power supply input for half-bridge output D 42 Copyright © 2007, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Link(s): TAS5706 |
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