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1OE

2OE

1EN

1

48

1CLK

1D

47

1D1

46

1D2

44

1D3

43

1D4

1Q1

2

1Q2

3

1Q3

5

1Q4

6

41

1D5

40

1D6

38

1D7

37

1D8

1Q5

8

1Q6

9

1Q7

11

1Q8

12

2D

36

2D1

35

2D2

33

2D3

32

2D4

2Q1

13

2Q2

14

2Q3

16

2Q4

17

30

2D5

29

2D6

27

2D7

26

2D8

2Q5

19

2Q6

20

2Q7

22

2Q8

23

2EN

24

25

2CLK

C1

C2

1

2

(1) This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

1OE

1CLK

1D1

To Seven Other Channels

1Q1

2OE

2CLK

2D1

2Q1

To Seven Other Channels

1

48

47

24

25

36

C1

1D

13

2

C1

1D

SN74ALVCH162374

16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP

WITH 3-STATE OUTPUTS

SCES092F – JANUARY 1997 – REVISED OCTOBER 2004

LOGIC DIAGRAM (POSITIVE LOGIC)

3