A squelching function can be created by sending the

CLKLOS output through an inverter to the OUTON pin.

This will squelch the CML outputs whenever the clock

signal is removed. A loss-of-signal LED indicator can

be incorporated into the circuit as well (see Figure 3).

Output Level Control (OUTLEVEL) Input

The OUTLEVEL pin is an LVTTL input that allows the

user to select between standard output amplitude

the standard output signal level, and forcing this pin

low results in the reduced output signal level.

Equalizer Control (EQCONTROL) Input

The EQCONTROL pin allows the user to control the

equalization in one of three ways: forcing the pin to

ground sets the equalizer in automatic equalization

minimum equalization, and forcing a voltage between

tion level applied to the input signals. See the

Typical

Operating Characteristics for more information.

Power-Down (PWRDWN) Input

The PWRDWN pin allows the part to be powered down

to reduce system power consumption. Force the pin

high for normal operation. Force the pin low to power-

down the IC. When powered down, the part consumes

approximately 10mA.

Output On (OUTON) Input

The OUTON pin is an LVTTL input. Force the pin low to

enable the outputs. Force the pin high to set a differential

zero on the outputs. When disabled, the outputs will go to

a differential zero, irrespective of the signal at the inputs.

Cable Selection

TMDS performance is heavily dependent on cable

quality. Deterministic jitter (DJ) can be caused by dif-

ferential-to-common-mode conversion (or vice-versa)

TMDS Digital Video Equalizer for DVI/HDMI

Cables

8

_______________________________________________________________________________________

MAX3815

RX_IN+/-

50

Ω

Figure 4. Simplified Input Circuit Schematic

MAX3815

RX_OUT+

RX_OUT-

Figure 5. Simplified Output Circuit Schematic

Interface Models

10k

Ω

4.7k

Ω

OUTON

200

Ω

LOSS-OF-CLOCK LED

CLKLOS

Figure 3. Squelch Circuit