M36W0R6050T1 datasheet(11/22 Pages) NUMONYX

Part #	M36W0R6050T1

Description	64 Mbit (4 Mb 횞16, Multiple Bank, Burst) Flash memory and 32 Mbit (2 Mb 횞16) PSRAM, multi-chip package

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Manufacturer	NUMONYX [Numonyx B.V]

Direct Link	http://www.numonyx.com

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M36W0R6050T1, M36W0R6050B1

Signal descriptions

11/22

2.12

PSRAM Chip Enable (E2P)

When de-asserted (Low), the Chip Enable input E2P, puts the device in Power-Down mode.

This is the lowest power mode according to the Configuration Register settings (see

M69KB048BD datasheet).

2.13

PSRAM Output Enable (GP)

The Output Enable, GP, provides a high speed tri-state control, allowing fast read/write

cycles to be achieved with the common I/O data bus.

2.14

PSRAM Write Enable (WP)

The Write Enable, WP, controls the Bus Write operation of the memory’s Command

Interface.

2.15

PSRAM Upper Byte Enable (UBP)

The Upper Byte Enable, UBP, gates the data on the Upper Byte Data Inputs/Outputs (DQ8-

DQ15) to or from the upper part of the selected address during a Write or Read operation.

2.16

PSRAM Lower Byte Enable (LBP)

The Lower Byte Enable, LBP, gates the data on the Lower Byte Data Inputs/Outputs (DQ0-

DQ7) to or from the lower part of the selected address during a Write or Read operation.

2.17

VDDF supply voltage

VDDF provides the power supply to the internal core of the Flash memory component. It is

the main power supplies for all Flash memory operations (Read, Program and Erase).

2.18

VDDP supply voltage

The VDDP Supply Voltage supplies the power for all operations (Read or Write) and for

driving the refresh logic, even when the device is not being accessed.

2.19

VDDQF supply voltage

VDDQF provides the power supply for the Flash memory I/O pins. This allows all Outputs to

be powered independently of the Flash memory core power supply, VDDF.

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