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M36W0R6050B1 Datasheet(PDF) 6 Page - Numonyx B.V |
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M36W0R6050B1 Datasheet(HTML) 6 Page - Numonyx B.V |
6 / 22 page Description M36W0R6050T1, M36W0R6050B1 6/22 1 Description The M36W0R6050T1 and M36W0R6050B1 combine two memories in a Multi-Chip Package: ● a 64-Mbit, Multiple Bank Flash memory, the M58WR064HT/B, and ● a 32-Mbit Pseudo SRAM, the M69KB048BD. The purpose of this document is to describe how the two memory components operate with respect to each other. It must be read in conjunction with the M58WR064HT/B and M69KB048BD datasheets, where all specifications required to operate the Flash memory and PSRAM components are fully detailed. These datasheets are available from the Numonyx web site: www.numonyx.com. Recommended operating conditions do not allow more than one memory to be active at the same time. The memory is offered in a Stacked TFBGA88 (8 ×10 mm, 8 × 10 ball array, 0.8 mm pitch) package. It is supplied with all the bits erased (set to ‘1’). Figure 1. Logic diagram Ai12035 22 A0-A21 DQ0-DQ15 M36W0R6050T1 M36W0R6050B1 GF 16 WF RPF WPF E1P GP WP UBP LBP VSS VDDF VPPF VDDP WAITF LF KF VDDQF EF E2P |
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Similar Description - M36W0R6050B1 |
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