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M58PR512LE Datasheet(PDF) 9 Page - Numonyx B.V |
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M58PR512LE Datasheet(HTML) 9 Page - Numonyx B.V |
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9 / 123 page  M58PR512LE, M58PR001LE Description 9/123 1 Description The M58PR512LE and M58PR001LE are 512 Mbit (32 Mbit x 16) and 1 Gbit (64 Mbit x 16) non-volatile flash memories. They are collectively referred to as the M58PRxxxLE in the rest of the document, unless otherwise specified. The M58PRxxxLE may be erased electrically at block level and programmed in-system on a word-by-word basis using a 1.7 V to 2.0 V VDD supply for the circuitry and a 1.7 V to 2.0 V VDDQ supply for the input/output pins. An optional 9 V VPP power supply is provided to speed up factory programming. The M58PRxxxLE has a uniform block architecture and is based on a multilevel cell technology: ● The M58PR512LE has an array of 256 blocks, and is divided into 64 Mbit banks. There are 8 banks each containing 32 blocks of 128 KWords. ● The M58PR001LE has an array of 512 blocks, and is divided into 128 Mbit banks. There are 8 banks each containing 64 blocks of 128 KWords. Each block contains 256 program regions of 1 Kbyte each, that are divided into 32 segments of 16 words. Each segment is split into two halves (A and B), according by the value on address input A3. The memory map is illustrated in Figure 4 and the main array architecture in Figure 5. The multiple bank architecture allows dual operations. While programming or erasing in one bank, read operations are possible in other banks. Only one bank at a time is allowed to be in program or erase mode. It is possible to perform burst reads that cross bank boundaries. The bank architectures are summarized in Table 2 and Table 3, and the memory maps are shown in Figure 4 and . Each block can be erased separately. Erase can be suspended to perform a program or read operation in any other block, and then resumed. Program can be suspended to read data at any memory location except for the one being programmed, and then resumed. Each block can be programmed and erased over 100 000 cycles using the supply voltage VDD. There is a buffer enhanced factory programming command available to speed up programming. Program and erase commands are written to the command interface of the memory. An internal Program/Erase Controller takes care of the timings necessary for program and erase operations. The end of a program or erase operation can be detected and any error conditions identified in the status register. The command set required to control the memory is consistent with JEDEC standards. The device supports synchronous burst read and asynchronous read from all blocks of the memory array; at power-up the device is configured for asynchronous read. In synchronous burst read mode, data is output on each clock cycle at frequencies of up to 108 MHz. The device features an automatic standby mode and deep power-down mode. When the bus is inactive during asynchronous read operations, the device automatically switches to automatic standby mode. In this state the power consumption is reduced to the standby value and the outputs are still driven. The DPD (deep power-down) mode starts when the device is properly configured (ECR bit 15 is set) and the DPD signal is asserted. In DPD mode the device has the lowest power consumption. |
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