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ISPLSI1016EA Datasheet(PDF) 3 Page - Lattice Semiconductor

Part No. ISPLSI1016EA
Description  In-System Programmable High Density PLD
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Maker  LATTICE [Lattice Semiconductor]
Homepage  http://www.latticesemi.com
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 3 page
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3
Specifications ispLSI 1016EA
Symbol
Parameter
Min
Max
Units
tbtcp
TCK [BSCAN test] clock pulse width
100
–
ns
tbtch
TCK [BSCAN test] pulse width high
50
–
ns
tbtcl
TCK [BSCAN test] pulse width low
50
–
ns
tbtsu
TCK [BSCAN test] setup time
20
–
ns
tbth
TCK [BSCAN test] hold time
25
–
ns
trf
TCK [BSCAN test] rise and fall time
50
–
mV/ns
tbtco
TAP controller falling edge of clock to valid output
–
25
ns
tbtoz
TAP controller falling edge of clock to data output disable
–
25
ns
tbtvo
TAP controller falling edge of clock to data output enable
–
25
ns
tbtcpsu
BSCAN test Capture register setup time
40
–
ns
tbtcph
BSCAN test Capture register hold time
25
–
ns
tbtuco
BSCAN test Update reg, falling edge of clock to valid output
–
50
ns
tbtuoz
BSCAN test Update reg, falling edge of clock to output disable
–
50
ns
tbtuov
BSCAN test Update reg, falling edge of clock to output enable
–
50
ns
Figure 2. Boundary Scan Waveforms and Timing Specifications
TMS
TDI
TCK
TDO
Data to be
captured
Data to be
driven out
Valid Data
Valid Data
Valid Data
Valid Data
Data Captured
btsu
T
bth
T
btcl
T
btch
T
btcp
T
btvo
T
btco
T
btoz
T
btcpsu
T
btcph
T
btuov
T
btuco
T
btuoz
T
Boundary Scan




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