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MM24128-BWMW6T Datasheet(PDF) 1 Page - STMicroelectronics |
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MM24128-BWMW6T Datasheet(HTML) 1 Page - STMicroelectronics |
1 / 17 page 1/17 June 2001 M24256 M24128 256/128 Kbit Serial I²C Bus EEPROM Without Chip Enable Lines s Compatible with I2C Extended Addressing s Two Wire I2C Serial Interface Supports 400 kHz Protocol s Single Supply Voltage: – 4.5V to 5.5V for M24xxx – 2.5V to 5.5V for M24xxx-W s Hardware Write Control s BYTE and PAGE WRITE (up to 64 Bytes) s RANDOM and SEQUENTIAL READ Modes s Self-Timed Programming Cycle s Automatic Address Incrementing s Enhanced ESD/Latch-Up Behavior s More than 100,000 Erase/Write Cycles s More than 40 Year Data Retention DESCRIPTION These I2C-compatible electrically erasable pro- grammable memory (EEPROM) devices are orga- nized as 32Kx8 bits (M24256) and 16Kx8 bits (M24128), and operate down to 2.5 V (for the -W version of each device). The M24256B, M24128B and M24256A are also available, and offer the extra functionality of the chip enable inputs. Please see the separate data sheets for details of these products. The M24256 and M24128 are available in Plastic Dual-in-Line and Plastic Small Outline packages. These memory devices are compatible with the I2C extended memory standard. This is a two wire Figure 1. Logic Diagram AI01882 SDA VCC M24256 M24128 WC SCL VSS Table 1. Signal Names SDA Serial Data/Address Input/ Output SCL Serial Clock WC Write Control VCC Supply Voltage VSS Ground PDIP8 (BN) 0.25 mm frame SO8 (MN) 150 mil width 8 1 8 1 SO8 (MW) 200 mil width 8 1 |
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