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MM24128-BMW5T Datasheet(PDF) 8 Page - STMicroelectronics |
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MM24128-BMW5T Datasheet(HTML) 8 Page - STMicroelectronics |
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8 / 17 page  M24256, M24128 8/17 the Device Select Code, with the RW bit set to ‘1’. The memory acknowledges this, and outputs the contents of the addressed byte. The master must not acknowledge the byte output, and terminates the transfer with a STOP condition. Current Address Read The device has an internal address counter which is incremented each time a byte is read. For the Current Address Read mode, following a START condition, the master sends a Device Select Code with the RW bit set to ‘1’. The memory acknowl- edges this, and outputs the byte addressed by the internal address counter. The counter is then in- minated the internal write cycle, it responds with an Ack, indicating that the memory is ready to receive the second part of the next instruction (the first byte of this instruction having been sent during Step 1). Read Operations Read operations are performed independently of the state of the WC pin. Random Address Read A dummy write is performed to load the address into the address counter, as shown in Figure 8. Then, without sending a STOP condition, the mas- ter sends another START condition, and repeats Figure 8. Read Mode Sequences Note: 1. The seven most significant bits of the Device Select Code of a Random Read (in the 1st and 4th bytes) must be identical. DEV SEL * BYTE ADDR BYTE ADDR DEV SEL DATA OUT 1 AI01105C DATA OUT N CURRENT ADDRESS READ DEV SEL DATA OUT RANDOM ADDRESS READ DEV SEL * DATA OUT SEQUENTIAL CURRENT READ DATA OUT N DEV SEL * BYTE ADDR BYTE ADDR SEQUENTIAL RANDOM READ DEV SEL * DATA OUT 1 ACK R/W NO ACK ACK R/W ACK ACK ACK R/W ACK ACK ACK NO ACK R/W NO ACK ACK ACK ACK R/W ACK ACK R/W ACK NO ACK |
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