NAND16GAH0D datasheet(9/116 Pages) NUMONYX

Part #	NAND16GAH0D

Description	1 Gbyte, 2 Gbyte, 1.8 V/3 V supply, NAND Flash memories with MultiMediaCard??interface

Download	116 Pages

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Manufacturer	NUMONYX [Numonyx B.V]

Direct Link	http://www.numonyx.com

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9 / 116 page

NAND08GAH0A, NAND16GAH0D

List of figures

9/116

List of figures

Figure 1.

Device block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 2.

LFBGA169 package connections (top view through package) . . . . . . . . . . . . . . . . . . . . . . 14

Figure 3.

Form factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 4.

Memory array structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 5.

Bus circuitry diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 6.

Power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 7.

Power cycling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 8.

Bus signal levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 9.

Timing diagram data input/output referenced to clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 10.

MultiMediaCard state diagram (Card Identification mode) . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 11.

Data transfer formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Figure 12.

MultiMediaCard state diagram (Data Transfer mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Figure 13.

Identification timing diagram (Card Identification mode). . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Figure 14.

SET_RCA timing diagram (Card Identification mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Figure 15.

Command response timing diagram (Data Transfer mode) . . . . . . . . . . . . . . . . . . . . . . . . 76

Figure 16.

R1b response timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Figure 17.

Last device response to Next Host command timing diagram . . . . . . . . . . . . . . . . . . . . . . 77

Figure 18.

Command n end to CMD n+1 start timing diagram (all modes) . . . . . . . . . . . . . . . . . . . . . 77

Figure 19.

Single Block Read command timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Figure 20.

Multiple Block Read command timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Figure 21.

STOP_TRANSMISSION command timing diagram (CMD12, Data Transfer mode) . . . . . 79

Figure 22.

Single Block Write command timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Figure 23.

Multiple Block Write command timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Figure 24.

STOP_TRANSMISSION during data transfer from the host timing diagram . . . . . . . . . . . 81

Figure 25.

STOP_TRANSMISSION during CRC status transfer from the device timing diagram . . . . 81

Figure 26.

STOP_TRANSMISSION received after last data block (device busy) . . . . . . . . . . . . . . . . 81

Figure 27.

STOP_TRANSMISSION received after last data block (device becomes busy) . . . . . . . . 81

Figure 28.

4-bit system bus test procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Figure 29.

SPI Single Block Read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Figure 30.

SPI Multiple Block Read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Figure 31.

SPI Read operation – data error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Figure 32.

SPI Single Block Write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Figure 33.

SPI Multiple Block Write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Figure 34.

Erase and Write Protect operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Figure 35.

R1 response format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Figure 36.

R1b response format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Figure 37.

R2 response format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

Figure 38.

R3 response format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

Figure 39.

Data response format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

Figure 40.

Data error message format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Figure 41.

Host command to device response timing diagram (device ready) . . . . . . . . . . . . . . . . . 107

Figure 42.

Host command to device response timing diagram (device busy) . . . . . . . . . . . . . . . . . . 107

Figure 43.

Device response to Host command timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Figure 44.

Single Block Read timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

Figure 45.

STOP_TRANSMISSION between blocks in Multiple Block Read timing diagram . . . . . . 108

Figure 46.

STOP_TRANSMISSION within a block in Multiple Block Read timing diagram . . . . . . . . 108

Figure 47.

CSD and CID register Read timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Figure 48.

Single Block Write timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

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