Electronic Components Datasheet Search
  English  ▼
ALLDATASHEET.NET

X  

TLK1002A Datasheet(PDF) 3 Page - Texas Instruments

Click here to check the latest version.
Part # TLK1002A
Description  DUAL SIGNAL CONDITIONING TRANSCEIVER
Download  16 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

TLK1002A Datasheet(HTML) 3 Page - Texas Instruments

  TLK1002A Datasheet HTML 1Page - Texas Instruments TLK1002A Datasheet HTML 2Page - Texas Instruments TLK1002A Datasheet HTML 3Page - Texas Instruments TLK1002A Datasheet HTML 4Page - Texas Instruments TLK1002A Datasheet HTML 5Page - Texas Instruments TLK1002A Datasheet HTML 6Page - Texas Instruments TLK1002A Datasheet HTML 7Page - Texas Instruments TLK1002A Datasheet HTML 8Page - Texas Instruments TLK1002A Datasheet HTML 9Page - Texas Instruments Next Button
Zoom Inzoom in Zoom Outzoom out
 3 / 16 page
background image
www.ti.com
LOW-NOISE HALF-RATE CLOCK GENERATION PLL
CONTROL INPUTS
REFERENCE VOLTAGE AND BIAS CURRENT GENERATION
PACKAGE
PIN OUT
RXA+
GND
TXA−
TXA+
GND
TXB−
GND
TXB+
RXB−
TLK1002A
RXA−
GND
RXB+
RGE PACKAGE
(TOP VIEW)
1
2
3
4
5
6
18
17
16
15
14
13
7 8 9 10 11 12
24 2322 21 20 19
TLK1002A
DUAL SIGNAL CONDITIONING TRANSCEIVER
SLLS661 – JUNE 2005
DATA PATHS (continued)
In order to achieve the low power requirements, an on-chip half-rate clock synthesizer PLL is implemented. It
generates the internally used inphase and quadrature clock signals with 5 times the reference clock frequency.
The required reference clock frequency equals approximately one tenth of the data rate. It may be off frequency
from both transmit and receive data streams by up to ±200 ppm.
A valid reference clock must be connected to the RCLK pin to ensure proper operation. In case of a clock
absence of up to 4 cycles during clock switch over the CDR will independently re-acquire lock (i.e., without the
need of any reset signal), however during re-locking erroneous bits will be transmitted for a limited period of time.
The reference clock may contain jitter, in the order of about 80 psp-p. However, the jitter components below 10
MHz, which is the bandwidth of the clock generation PLL, must not exceed 40 psp-p.
Increased reference clock jitter leads to increased output jitter as well as to reduced jitter tolerance.
TLK1002A provides a total of four control inputs, which activate the VML output buffer stages and enable the
loop-back modes.
These control inputs may be driven from circuits using a different supply voltage. Thus, 2.5 V tolerance is
mandatory at these pins. All control inputs provide on-chip pull-up resistors to VDD.
The TLK1002A transceiver is supplied by a 1.8 V ±5% supply voltage connected to VDD. The voltage is referred
to ground (GND).
From this voltage all required reference voltages and bias currents are derived by means of the reference voltage
and bias current generation block.
For the TLK1002A a small footprint 4 mm × 4 mm 24-lead QFN package is used, with a lead pitch of 0.5 mm.
The pin out is shown below.
The thermal resistance of the package is about 47°C/W. At a total power consumption of 0.3 W assuming an
ambient temperature of 70°C, the maximum junction temperature is below 85°C.
3


Similar Part No. - TLK1002A

ManufacturerPart #DatasheetDescription
logo
Texas Instruments
TLK10021ZWQ TI1-TLK10021ZWQ Datasheet
658Kb / 2P
[Old version datasheet]   10 Gbps PHY Transceiver for LAN/MAN/SAN Applications
TLK10022 TI1-TLK10022 Datasheet
566Kb / 64P
[Old version datasheet]   10Gbps DUAL-CHANNEL MULTI-RATE SERIAL LINK AGGREGATOR
TLK10022CTR TI1-TLK10022CTR Datasheet
566Kb / 64P
[Old version datasheet]   10Gbps DUAL-CHANNEL MULTI-RATE SERIAL LINK AGGREGATOR
More results

Similar Description - TLK1002A

ManufacturerPart #DatasheetDescription
logo
List of Unclassifed Man...
SA40011 ETC1-SA40011 Datasheet
394Kb / 2P
   Dual Axis Signal Conditioning Module
logo
Analog Devices
AD7711 AD-AD7711_17 Datasheet
354Kb / 29P
   Signal Conditioning ADC
AD7714 AD-AD7714_17 Datasheet
349Kb / 41P
   Signal Conditioning ADC
logo
MORNSUN Science& Techno...
T797HL MORNSUN-T797HL_15 Datasheet
1Mb / 6P
   Signal conditioning module
logo
Analog Devices
AD7712 AD-AD7712_15 Datasheet
258Kb / 28P
   Signal Conditioning ADC
REV. F
logo
Honeywell Solid State E...
DC005NDC4 HONEYWELL-DC005NDC4 Datasheet
129Kb / 4P
   Signal Conditioning: Amplified
logo
Analog Devices
AD7710AR-REEL7 AD-AD7710AR-REEL7 Datasheet
265Kb / 32P
   Signal Conditioning ADC
REV. G
AD7714 AD-AD7714_15 Datasheet
298Kb / 40P
   Signal Conditioning ADC
REV. C
AD7710 AD-AD7710_15 Datasheet
265Kb / 32P
   Signal Conditioning ADC
REV. G
logo
MORNSUN Science& Techno...
TF5134N MORNSUN-TF5134N_15 Datasheet
306Kb / 5P
   Signal conditioning modules
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16


Datasheet Download

Go To PDF Page


Link URL




Privacy Policy
ALLDATASHEET.NET
Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com