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TLK1002A Datasheet(PDF) 3 Page - Texas Instruments |
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TLK1002A Datasheet(HTML) 3 Page - Texas Instruments |
3 / 16 page www.ti.com LOW-NOISE HALF-RATE CLOCK GENERATION PLL CONTROL INPUTS REFERENCE VOLTAGE AND BIAS CURRENT GENERATION PACKAGE PIN OUT RXA+ GND TXA− TXA+ GND TXB− GND TXB+ RXB− TLK1002A RXA− GND RXB+ RGE PACKAGE (TOP VIEW) 1 2 3 4 5 6 18 17 16 15 14 13 7 8 9 10 11 12 24 2322 21 20 19 TLK1002A DUAL SIGNAL CONDITIONING TRANSCEIVER SLLS661 – JUNE 2005 DATA PATHS (continued) In order to achieve the low power requirements, an on-chip half-rate clock synthesizer PLL is implemented. It generates the internally used inphase and quadrature clock signals with 5 times the reference clock frequency. The required reference clock frequency equals approximately one tenth of the data rate. It may be off frequency from both transmit and receive data streams by up to ±200 ppm. A valid reference clock must be connected to the RCLK pin to ensure proper operation. In case of a clock absence of up to 4 cycles during clock switch over the CDR will independently re-acquire lock (i.e., without the need of any reset signal), however during re-locking erroneous bits will be transmitted for a limited period of time. The reference clock may contain jitter, in the order of about 80 psp-p. However, the jitter components below 10 MHz, which is the bandwidth of the clock generation PLL, must not exceed 40 psp-p. Increased reference clock jitter leads to increased output jitter as well as to reduced jitter tolerance. TLK1002A provides a total of four control inputs, which activate the VML output buffer stages and enable the loop-back modes. These control inputs may be driven from circuits using a different supply voltage. Thus, 2.5 V tolerance is mandatory at these pins. All control inputs provide on-chip pull-up resistors to VDD. The TLK1002A transceiver is supplied by a 1.8 V ±5% supply voltage connected to VDD. The voltage is referred to ground (GND). From this voltage all required reference voltages and bias currents are derived by means of the reference voltage and bias current generation block. For the TLK1002A a small footprint 4 mm × 4 mm 24-lead QFN package is used, with a lead pitch of 0.5 mm. The pin out is shown below. The thermal resistance of the package is about 47°C/W. At a total power consumption of 0.3 W assuming an ambient temperature of 70°C, the maximum junction temperature is below 85°C. 3 |
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