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C1608X7R1H472K Datasheet(PDF) 7 Page - International Rectifier

Part # C1608X7R1H472K
Description  500kHz, 40A, 2-phase Synchronous Buck Converter using iP2001
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Manufacturer  IRF [International Rectifier]
Direct Link  http://www.irf.com
Logo IRF - International Rectifier

C1608X7R1H472K Datasheet(HTML) 7 Page - International Rectifier

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7
IRDCiP2001-A
Sequencing Tip
It’s important to have proper sequencing between the control IC and the iP2001 blocks. This assures the soft-start
routine of the IC will properly ramp-up the output voltage during a power-up or restart from shut down event. Figure
7 shows a simple and cost effective way to synchronize the iP2001 blocks with an HIP6311 control IC in a 2 Phase
configuration.
Placing Schottky diodes between the iP2001’s PRDY pin and the IC’s FS/DIS pin creates an interface analogous to an
AND operation. With this configuration, no single iP2001 can enable the IC independently. This configuration also
resolves any differences in timing and logic thresholds between iP2001 devices. The capacitors are used to filter
high frequency noise on the PRDY line. Additionally, the ENABLE pin of the iP2001 blocks can be used as the master
control switch for the system.
During power-up, the PRDY pin is held low until V
DD reaches a typical voltage of 4.4V. Until then, the schottky diode is
forward biased and clamps the FS/DIS pin well below the disable voltage of the HIP6311 IC (typically 1V). Upon
reaching 4.4V, the PRDY pin transitions to a logic-level high state and releases the clamp on the FS/DIS pin. This
enables the IC and allows its soft start routine to begin (see figure 8), assuming the voltage at the IC’s V
CC pin is
greater than its power-on reset threshold.
When the ENABLE pin is held to a logic-level low state (shut down mode), the PRDY pin clamps the FS/DIS pin of the
IC below the disable voltage. After the ENABLE pin transitions to a logic-level high state, the PRDY releases the
clamp on the FS/DIS pin, enabling the IC and allowing its soft start routine to begin (see figure 9).
During power-down, the PRDY pin transitions to a logic-level low state when the V
DD reaches the under voltage lock
out threshold of the iP2001 blocks. The FS/DIS pin is then clamped below the disable voltage, disabling the control IC.
Fig. 7 - Sequencing Schematic
51k
VSEN
GND
FS/DIS
FB
COMP
PWM3
ISEN3
ISEN2
PWM2
PWM1
HIP6311
BAT54
BAT54
ENABLE
PRDY1
ENABLE
iP2001
iP2001
PRDY2
Master
Control
0.22µF
0.22µF


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