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TMS320F28235 Datasheet(PDF) 2 Page - Texas Instruments |
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TMS320F28235 Datasheet(HTML) 2 Page - Texas Instruments |
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2 / 170 page  Contents TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 Digital Signal Controllers (DSCs) SPRS439C – JUNE 2007 – REVISED FEBRUARY 2008 Revision History .......................................................................................................................... 11 1 TMS320F2833x, TMS320F2823x DSCs ................................................................................... 13 1.1 Features ..................................................................................................................... 13 1.2 Getting Started .............................................................................................................. 14 2 Introduction ....................................................................................................................... 15 2.1 Pin Assignments ............................................................................................................ 17 2.2 Signal Descriptions ......................................................................................................... 26 3 Functional Overview ........................................................................................................... 35 3.1 Memory Maps .............................................................................................................. 36 3.2 Brief Descriptions ........................................................................................................... 42 3.2.1 C28x CPU ....................................................................................................... 42 3.2.2 Memory Bus (Harvard Bus Architecture) .................................................................... 43 3.2.3 Peripheral Bus .................................................................................................. 43 3.2.4 Real-Time JTAG and Analysis ................................................................................ 43 3.2.5 External Interface (XINTF) ..................................................................................... 43 3.2.6 Flash .............................................................................................................. 44 3.2.7 M0, M1 SARAMs ............................................................................................... 44 3.2.8 L0, L1, L2, L3, L4, L5, L6, L7 SARAMs ..................................................................... 44 3.2.9 Boot ROM ........................................................................................................ 44 3.2.10 Security .......................................................................................................... 45 3.2.11 Peripheral Interrupt Expansion (PIE) Block .................................................................. 46 3.2.12 External Interrupts (XINT1-XINT7, XNMI) .................................................................... 47 3.2.13 Oscillator and PLL .............................................................................................. 47 3.2.14 Watchdog ........................................................................................................ 47 3.2.15 Peripheral Clocking ............................................................................................. 47 3.2.16 Low-Power Modes .............................................................................................. 47 3.2.17 Peripheral Frames 0, 1, 2, 3 (PFn) ........................................................................... 47 3.2.18 General-Purpose Input/Output (GPIO) Multiplexer ......................................................... 48 3.2.19 32-Bit CPU-Timers (0, 1, 2) ................................................................................... 48 3.2.20 Control Peripherals ............................................................................................. 48 3.2.21 Serial Port Peripherals ......................................................................................... 48 3.3 Register Map ................................................................................................................ 49 3.4 Device Emulation Registers ............................................................................................... 50 3.5 Interrupts .................................................................................................................... 52 3.5.1 External Interrupts .............................................................................................. 56 3.6 System Control ............................................................................................................. 56 3.6.1 OSC and PLL Block ............................................................................................ 58 3.6.1.1 External Reference Oscillator Clock Option ....................................................... 59 3.6.1.2 PLL-Based Clock Module ............................................................................ 59 3.6.1.3 Loss of Input Clock ................................................................................... 61 3.6.2 Watchdog Block ................................................................................................. 61 3.7 Low-Power Modes Block .................................................................................................. 62 4 Peripherals ........................................................................................................................ 63 4.1 DMA Overview .............................................................................................................. 64 4.2 32-Bit CPU-Timers 0/1/2 .................................................................................................. 65 4.3 Enhanced PWM Modules (ePWM1/2/3/4/5/6) .......................................................................... 67 4.4 High-Resolution PWM (HRPWM) ........................................................................................ 69 4.5 Enhanced CAP Modules (eCAP1/2/3/4/5/6) ............................................................................ 70 4.6 Enhanced QEP Modules (eQEP1/2) ..................................................................................... 72 4.7 Analog-to-Digital Converter (ADC) Module ............................................................................. 74 Contents 2 Submit Documentation Feedback |
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