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74AUP1G157 Datasheet(PDF) 3 Page - NXP Semiconductors |
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74AUP1G157 Datasheet(HTML) 3 Page - NXP Semiconductors |
3 / 16 page 74AUP1G157_1 © NXP B.V. 2006. All rights reserved. Product data sheet Rev. 01 — 9 November 2006 3 of 16 NXP Semiconductors 74AUP1G157 Low-power 2-input multiplexer 6. Pinning information 6.1 Pinning 6.2 Pin description Fig 4. Logic diagram 001aac654 Y S I1 I0 Fig 5. Pin configuration SOT363 (SC-88) Fig 6. Pin configuration SOT886 (XSON6) Fig 7. Pin configuration SOT891 (XSON6) 74AUP1G157 I1 S GND I0 Y 001aae015 1 2 3 6 VCC 5 4 74AUP1G157 GND 001aae016 I1 I0 VCC S Y Transparent top view 2 3 1 5 4 6 74AUP1G157 GND 001aae017 I1 I0 VCC S Y Transparent top view 2 3 1 5 4 6 Table 3. Pin description Symbol Pin Description I1 1 data input from source 1 GND 2 ground (0 V) I0 3 data input from source 0 Y 4 multiplexer output VCC 5 supply voltage S 6 common data select input |
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