M36W432B datasheet(6/57 Pages) STMICROELECTRONICS

Part #	M36W432B

Description	32 Mbit 2Mb x16, Boot Block Flash Memory and 4 Mbit 256K x16 SRAM, Multiple Memory Product

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Manufacturer	STMICROELECTRONICS [STMicroelectronics]

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M36W432T, M36W432B

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Figure 3. LFBGA Connections (Top view through package)

SIGNAL DESCRIPTIONS

See Figure 2 Logic Diagram and Table 1,Signal

Names, for a brief overview of the signals connect-

ed to this device.

Address Inputs (A0-A17). Addresses

A0-A17

are common inputs for the Flash and the SRAM

components. The Address Inputs select the cells

in the memory array to access during Bus Read

operations. During Bus Write operations they con-

trol the commands sent to the Command Interface

of the internal state machine. The Flash memory is

accessed through the Chip Enable (EF)and Write

Enable (WF) signals, while the SRAM is accessed

through two Chip Enable signals (E1S and E2S)

and the Write Enable signal (WS).

Address Inputs (A18-A20). Addresses A18-A20

are inputs for the Flash component only. The

Flash memory is accessed through the Chip En-

able (EF) and Write Enable (WF) signals

Data Input/Output (DQ0-DQ15). The Data I/O

outputs the data stored at the selected address

during a Bus Read operation or inputs a command

or thedatatobeprogrammedduringa WriteBus

operation.

Flash Chip Enable (EF). The Chip Enable input

activates the Flash memory control logic, input

buffers, decoders and sense amplifiers. When

Chip Enable is at VIL and ResetisatVIH the device

is in active mode. When Chip Enable is at VIH the

memory is deselected, the outputs are high imped-

ance and the power consumption is reduced to the

standby level.

Flash Output Enable (GF). The Output Enable

controls the data outputs during the Bus Read op-

eration of the Flash memory.

Flash Write Enable (WF). The

Write

Enable

controls the Bus Write operation of the Flash

memory’s Command Interface. The data and ad-

dress inputs are latched on the rising edge of Chip

Enable, EF, or Write Enable, WF, whichever oc-

curs first.

AI05201

A

6

5

4

3

2

1

#2

#1

E

B

F

A12

A13

A11

A20

NC

E2S

DQ12

VSSS

A2

A3

A6

A7

A18

EF

A0

A4

NC

DQ4

WS

DQ15

A9

A16

DQ6

DQ13

NC

WF

A8

A10

A5

NC

VSSF

A17

RPF

A15

A14

NC

VDDF

E1S

A1

NC

GF

VDDS

DQ7

DQ5

DQ14

NC

VSSF

VDDQF

#4

#3

8

7

C

DQ10

DQ11

A19

WPF

VPPF

DQ3

DQ2

D

DQ8

DQ9

GS

LBS

UBS

DQ1

DQ0

G

H

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