M36DR432DA10ZA6T datasheet(5/46 Pages) STMICROELECTRONICS

Part #	M36DR432DA10ZA6T

Description	32 Mbit 2Mb x16, Dual Bank, Page Flash Memory and 4 Mbit 256K x16 SRAM, Multiple Memory Product

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Manufacturer	STMICROELECTRONICS [STMicroelectronics]

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M36DR432C, M36DR432D

SIGNAL DESCRIPTIONS

See Figure 2 and Table 1.

Address Inputs (A0-A17). Addresses A0 to A17

are common inputs for the Flash chip and the

SRAM chip. The address inputs for the Flash

memory are latched during a write operation on

the falling edge of the Flash Chip Enable (EF)or

Write Enable (WF), while address inputs for the

SRAM array are latched during a write operation

on the falling edge of the SRAM Chip Enable lines

(E1S or E2S) or Write Enable (WS).

Address Inputs (A18-A20). Address A18 to A20

are address inputs for the Flash chip. They are

latched during a write operation on the falling edge

of Flash Chip Enable (EF) or Write Enable (WF).

Data Input/Outputs (DQ0-DQ15). The input is

data to be programmed in the Flash or SRAM

memory array or a command to be written to the

C.I. of the Flash chip. Both are latched on the ris-

ing edge of Flash Chip Enable (EF)orWrite En-

able (WF) and, SRAM Chip Enable lines (E1S or

E2S) or Write Enable (WS). The output is data

from the Flash memory or SRAM array, the Elec-

tronic Signature Manufacturer or Device codes or

the Status register Data Polling bit DQ7, the Tog-

gle Bits DQ6 and DQ2, the Error bit DQ5 or the

Erase Timer bit DQ3. Outputs are valid when

Flash Chip Enable (EF) and Output Enable (GF)or

SRAM Chip Enable lines (E1S or E2S) and Output

Enable (GS) are active. The output is high imped-

ance when the both the Flash chip and the SRAM

chip are deselected or the outputs are disabled

and when Reset (RPF)is at a VIL.

Flash Chip Enable (EF). The Chip Enable input

for Flash activates the memory control logic, input

buffers, decoders and sense amplifiers. EF at VIH

deselects the memory and reduces the power con-

sumption to the standby level and output do Hi-Z.

EF canalsobeusedto control writing to the com-

mand register and to the Flash memory array,

while WF remains at VIL.Itisnot allowed to set EF

at VIL,E1S at VIL and E2S at VIH at the same time.

Flash Write Enable (WF). The Write Enable in-

put controls writing to the Command Register of

the Flash chip and Address/Data latches. Data are

latched on the rising edge of WF.

Flash Output Enable (GF). The Output Enable

gates the outputs through the data buffers during

a read operation of the Flash chip. When GF and

WF are High the outputs are High impedance.

Flash Reset/Power Down Input (RPF). The RPF

input provides hardware reset of the memory

(without affecting the Configuration Register sta-

tus), and/or Power Down functions, depending on

the Configuration Register status. Reset/Power

Down of the memory is achieved by pulling RPF to

VIL for at least tPLPH. When the reset pulse is giv-

en, if the memory is in Read, Erase Suspend Read

or Standby, it will output new valid data in tPHQ7V1

after the rising edge of RPF.Ifthe memory is in

Erase or Program modes, the operation will be

aborted and the reset recovery will take a maxi-

mum of tPLQ7V. The memory will recover from

Power Down (when enabled) in tPHQ7V2 after the

rising edge of RPF. See Tables 1, 26 and Figure

11.

Flash Write Protect (WPF). Write Protect is an

input to protect or unprotect the two lockable pa-

rameter blocks of the Flash memory. When WPF

is at VIL, the lockable blocks are protected. Pro-

gram or erase operations are not achievable.

When WPF is at VIH, the lockable blocks are un-

protected and they can be programmed or erased

(refer to Table 17).

SRAM Chip Enable (E1S,E2S). The Chip En-

able inputs for SRAM activate the memory control

logic, input buffers and decoders. E1S at VIH or

E2S at VIL deselects the memory and reduces the

power consumption to the standby level. E1S and

E2S can also be used to control writing to the

SRAM memory array, while WS remains at VIL.It

is not allowed to set EF at VIL,E1S at VIL and E2S

at VIH at the same time.

SRAM WriteEnable(WS). The Write Enable in-

put controls writing to the SRAM memory array.

WS is active low.

SRAM Output Enable (GS). The Output Enable

gates the outputs through the data buffers during

a read operation of the SRAM chip. GS is active

low.

SRAM Upper Byte Enable (UBS). Enable

the

upper bytes for SRAM (DQ8-DQ15). UBS is active

low.

SRAM Lower Byte Enable (LBS). Enable

the

lower bytes for SRAM (DQ0-DQ7). LBS is active

low.

VDDF Supply Voltage (1.9V to 2.1V). Flash memory

power supply for all operations (Read, Program and

Erase).

VPPF Programming Voltage (11.4V to 12.6V).

Used to provide high voltage for fast factory pro-

gramming. High voltage on VPPF pin is required to

use the Double Word Program instruction. It is

also possible to perform word program or erase in-

structions with VPPF pin grounded.

VDDS Supply Voltage (1.9V to 2.1V). SRAM pow-

er supply for all operations (Read, Program).

VSSF and VSSS Ground. VSSF and VSSS are the

reference for all voltage measurements respec-

tively in the Flash and SRAM chips.

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