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M36W832BEZA Datasheet(PDF) 11 Page - STMicroelectronics |
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M36W832BEZA Datasheet(HTML) 11 Page - STMicroelectronics |
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11 / 64 page  11/64 M36W832TE, M36W832BE Flash Memory Component The Flash Memory is a 32 Mbit (2 Mbit x 16) device that can be erased electrically at block level and programmed in-system on a Word-by-Word basis. These operations can be performed using a single low voltage (2.7 to 3.6V) supply. VDDQF allows to drive the I/O pin down to 1.65V. An optional 12V VPPF power supply is provided to speed up cus- tomer programming. The device features an asymmetrical blocked ar- chitecture with an array of 71 blocks: 8 Parameter Blocks of 4 KWords and 63 Main Blocks of 32 KWords. The M36W832TE has the Parameter Blocks at the top of the memory address space while the M36W832BE locates the Parameter Blocks starting from the bottom. The memory maps are shown in Figure 5, Block Addresses. The Flash Memory features an instant, individual block locking scheme that allows any block to be locked or unlocked with no latency, enabling in- stant code and data protection. All blocks have three levels of protection. They can be locked and locked-down individually preventing any acciden- tal programming or erasure. There is an additional hardware protection against program and erase. When VPPF ≤ VPPLK all blocks are protected against program or erase. All blocks are locked at Power Up. Each block can be erased separately. Erase can be suspended in order to perform either read or program in any other block and then resumed. Program can be suspended to read data in any other block and then resumed. Each block can be programmed and erased over 100,000 cycles. The device includes a Protection Register to in- crease the protection of a system design. The Pro- tection Register is divided into two segments, the first is a 64 bit area which contains a unique device number written by ST, while the second is a 128 bit area, one-time-programmable by the user. The user programmable segment can be permanently protected. Figure 6, shows the Flash Security Block and Protection Register Memory Map. Program and Erase commands are written to the Command Interface of the memory. An on-chip Program/Erase Controller takes care of the tim- ings necessary for program and erase operations. The end of a program or erase operation can be detected and any error conditions identified. The command set required to control the memory is consistent with JEDEC standards. Figure 5. Flash Block Addresses Note: Also see Appendix A, Tables 26 and 27 for a full listing of the Flash Block Addresses. AI90164 4 KWords 1FFFFF 1FF000 32 KWords 00FFFF 008000 32 KWords 007FFF 000000 Top Boot Block Addresses 4 KWords 1F8FFF 1F8000 32 KWords 1F0000 1F7FFF Total of 8 4 KWord Blocks Total of 63 32 KWord Blocks 4 KWords 1FFFFF 1F8000 32 KWords 32 KWords 000FFF 000000 Bottom Boot Block Addresses 4 KWords 1F7FFF 00FFFF 32 KWords 1F0000 008000 Total of 63 32 KWord Blocks Total of 8 4 KWord Blocks 007FFF 007000 |
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