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M36W108AB100ZN1T Datasheet(PDF) 7 Page - STMicroelectronics |
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M36W108AB100ZN1T Datasheet(HTML) 7 Page - STMicroelectronics |
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7 / 36 page  7/36 M36W108AT, M36W108AB Write. Write operations are used to give Instruc- tion Commands to the memory or to latch input data to be programmed. A write operation is initi- ated when Chip Enable (EF) is Low and Write En- able (W) is at VIL with Output Enable (G) at VIH. Addresses are latched on the falling edge of W or EF whichever occurs last. Commands and Input Data are latched on the rising edge of W or EF whichever occurs first. Output Disable. The data outputs are high im- pedance when the Output Enable (G) is at VIH with Write Enable (W) at VIH. Standby. The memory is in standby when Chip Enable (EF) is at VIH and the P/E.C. is idle. The power consumption is reduced to the standby level and the outputs are high impedance, independent of the Output Enable (G) or Write Enable (W) in- puts. Automatic Standby. After 150ns of bus inactivity and when CMOS levels are driving the addresses, the chip automatically enters a pseudo-standby mode where consumption is reduced to the CMOS standby value, while outputs still drive the bus. Instructions and Commands Seven instructions are defined (see Table 7) to perform Read Array, Auto Select (to read the Elec- tronic Signature), Program, Block Erase, Chip Erase, Erase Suspend and Erase Resume. The internal P/E.C. automatically handles all timing and verification of the Program and Erase opera- tions. The Status Register Data Polling, Toggle, Error bits and the RB output may be read at any time, during programming or erase, to monitor the progress of the operation. Instructions, made up of commands written in cy- cles, can be given to the Program/Erase Controller through a Command Interface (C.I.). The C.I. latches commands written to the memory. Commands are made of address and data se- quences. Two coded cycles unlock the Command Interface. They are followed by an input command or a confirmation command. The coded sequence consists of writing the data AAh at the address 5555h during the first cycle and the data 55h at the address 2AAAh during the second cycle. Table 6. Flash User Bus Operations (1) Note: 1. X = VIL or VIH. Table 7. Read Flash Electronic Signature Operation EF G W RP A15 A12 A9 A6 A1 A0 DQ7-DQ0 Read Byte VIL VIL VIH VIH A15 A12 A9 A6 A1 A0 Data Output Write Byte VIL VIH VIL VIH A15 A12 A9 A6 A1 A0 Data Input Output Disable VIL VIH VIH VIH XXXXXX Hi-Z Stand-by VIH XX VIH XXXXXX Hi-Z Reset X X X VIL XXXXXX Hi-Z Code Device EF G W A1 A0 Other Addresses DQ7-DQ0 Manufact. Code VIL VIL VIH VIL VIL Don’t care 20h Device Code M36W108AT VIL VIL VIH VIL VIH Don’t care D2h M36W108AB VIL VIL VIH VIL VIH Don’t care DCh |
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