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M36WV8B85ZA6T Datasheet(PDF) 9 Page - STMicroelectronics |
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M36WV8B85ZA6T Datasheet(HTML) 9 Page - STMicroelectronics |
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9 / 92 page  9/92 M36WT864TF, M36WT864BF SIGNAL DESCRIPTIONS See Figure 2 Logic Diagram and Table 1,Signal Names, for a brief overview of the signals connect- ed to this device. Address Inputs (A0-A18). Addresses A0-A18 are common inputs for the Flash and the SRAM components. The Address Inputs select the cells in the memory array to access during Bus Read operations. During Bus Write operations they con- trol the commands sent to the Command Interface of the internal state machine. The Flash memory is accessed through the Chip Enable (EF) and Write Enable (WF) signals, while the SRAM is accessed through two Chip Enable signals (E1S and E2S) and the Write Enable signal (WS). Address Inputs (A19-A21). Addresses A19-A21 are inputs for the Flash component only. The Flash memory is accessed through the Chip En- able (EF) and Write Enable (WF) signals. Data Input/Output (DQ0-DQ15). The Data I/O outputs the data stored at the selected address during a Bus Read operation or inputs a command or the data to be programmed during a Write Bus operation. Flash Chip Enable (EF). The Chip Enable input activates the memory control logic, input buffers, decoders and sense amplifiers. When Chip En- able is at VILand Reset is at VIH the device is in ac- tive mode. When Chip Enable is at VIH the memory is deselected, the outputs are high imped- ance and the power consumption is reduced to the stand-by level. Flash Output Enable (GF). The Output Enable controls data outputs during the Bus Read opera- tion of the memory. Flash Write Enable (WF). The Write Enable controls the Bus Write operation of the memory’s Command Interface. The data and address inputs are latched on the rising edge of Chip Enable or Write Enable whichever occurs first. Flash Write Protect (WPF). Write Protect is an input that gives an additional hardware protection for each block. When Write Protect is at VIL, the Lock-Down is enabled and the protection status of the Locked-Down blocks cannot be changed. When Write Protect is at VIH, the Lock-Down is disabled and the Locked-Down blocks can be locked or unlocked. (refer to Table 13, Lock Sta- tus). Flash Reset (RPF). The Reset input provides a hardware reset of the memory. When Reset is at VIL, the memory is in reset mode: the outputs are high impedance and the current consumption is reduced to the Reset Supply Current IDD2. Refer to Table 2, DC Characteristics - Currents for the val- ue of IDD2. After Reset all blocks are in the Locked state and the Configuration Register is reset. When Reset is at VIH, the device is in normal op- eration. Exiting reset mode the device enters asynchronous read mode, but a negative transi- tion of Chip Enable or Latch Enable is required to ensure valid data outputs. The Reset pin can be interfaced with 3V logic with- out any additional circuitry. It can be tied to VRPH (refer to Table 19, DC Characteristics). Flash Latch Enable (LF). Latch Enable latches the address bits on its rising edge. The address latch is transparent when Latch Enable is at VIL and it is inhibited when Latch Enable is at VIH. Latch Enable can be kept Low (also at board level) when the Latch Enable function is not required or supported. Flash Clock (KF). The clock input synchronizes the Flash memory to the microcontroller during synchronous read operations; the address is latched on a Clock edge (rising or falling, accord- ing to the configuration settings) when Latch En- able is at VIL. Clock is don't care during asynchronous read and in write operations. Flash Wait (WAITF). Wait is a Flash output signal used during synchronous read to indicate whether the data on the output bus are valid. This output is high impedance when Flash Chip Enable is at VIH or Flash Reset is at VIL. It can be configured to be active during the wait cycle or one clock cycle in advance. The WAITF signal is not gated by Output Enable. SRAM Chip Enable (E1S, E2S). The Chip En- able inputs activate the SRAM memory control logic, input buffers and decoders. E1S at VIH or E2S at VIL deselects the memory and reduces the power consumption to the standby level. E1S and E2S can also be used to control writing to the SRAM memory array, while WS remains at VIL. It is not allowed to set EF at VIL, E1S at VIL and E2S at VIH at the same time. SRAM Write Enable (WS). The Write Enable in- put controls writing to the SRAM memory array. WS is active low. SRAM Output Enable (GS). The Output Enable gates the outputs through the data buffers during a read operation of the SRAM memory. GS is ac- tive low. SRAM Upper Byte Enable (UBS). The Upper Byte Enable input enables the upper byte for SRAM (DQ8-DQ15). UBS is active low. SRAM Lower Byte Enable (LBS). The Lower Byte Enable input enables the lower byte for SRAM (DQ0-DQ7). LBS is active low. VDDF Supply Voltage. VDDF provides the power supply to the internal core of the Flash memory de- |
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