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M36W832TE85ZA6S Datasheet(PDF) 8 Page - STMicroelectronics

Part # M36W832TE85ZA6S
Description  32 Mbit 2Mb x16, Boot Block Flash Memory and 8 Mbit 512Kb x16 SRAM, Multiple Memory Product
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

M36W832TE85ZA6S Datasheet(HTML) 8 Page - STMicroelectronics

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Signal Descriptions
See Figure 2 Logic Diagram and Table 1,Signal
Names, for a brief overview of the signals connect-
ed to this device.
Address Inputs (A0-A18). Addresses
A0-A18
are common inputs for the Flash and the SRAM
components. The Address Inputs select the cells
in the memory array to access during Bus Read
operations. During Bus Write operations they con-
trol the commands sent to the Command Interface
of the internal state machine. The Flash memory is
accessed through the Chip Enable (EF) and Write
Enable (WF) signals, while the SRAM is accessed
through two Chip Enable signals (E1S and E2S)
and the Write Enable signal (WS).
Address Inputs (A19-A20). Addresses A19-A20
are inputs for the Flash component only. The
Flash memory is accessed through the Chip En-
able (EF) and Write Enable (WF) signals
Data Input/Output (DQ0-DQ15). The Data I/O
outputs the data stored at the selected address
during a Bus Read operation or inputs a command
or the data to be programmed during a Write Bus
operation.
Flash Chip Enable (EF). The Chip Enable input
activates the Flash memory control logic, input
buffers, decoders and sense amplifiers. When
Chip Enable is at VIL and Reset is at VIH the device
is in active mode. When Chip Enable is at VIH the
memory is deselected, the outputs are high imped-
ance and the power consumption is reduced to the
standby level.
Flash Output Enable (GF). The Output Enable
controls the data outputs during the Bus Read op-
eration of the Flash memory.
Flash Write Enable (WF). The
Write
Enable
controls the Bus Write operation of the Flash
memory’s Command Interface. The data and ad-
dress inputs are latched on the rising edge of Chip
Enable, EF, or Write Enable, WF, whichever oc-
curs first.
Flash Write Protect (WPF). Write Protect is an
input that gives an additional hardware protection
for each block. When Write Protect is at VIL, the
Lock-Down is enabled and the protection status of
the block cannot be changed. When Write Protect
is at VIH, the Lock-Down is disabled and the block
can be locked or unlocked. (refer to Table 6, Read
Protection Register and Protection Register Lock).
Flash Reset (RPF). The Reset input provides a
hardware reset of the Flash memory. When Reset
is at VIL, the memory is in reset mode: the outputs
are high impedance and the current consumption
is minimized. After Reset all blocks are in the
Locked state. When Reset is at VIH, the device is
in normal operation. Exiting reset mode the device
enters read array mode, but a negative transition
of Chip Enable or a change of the address is re-
quired to ensure valid data outputs.
SRAM Chip Enable (E1S, E2S). The Chip En-
able inputs activate the SRAM memory control
logic, input buffers and decoders. E1S at VIH or
E2S at VIL deselects the memory and reduces the
power consumption to the standby level. E1S and
E2S can also be used to control writing to the
SRAM memory array, while WS remains at VIL. It
is not allowed to set EF at VIL, E1S at VIL and E2S
at VIH at the same time.
SRAM Write Enable (WS). The Write Enable in-
put controls writing to the SRAM memory array.
WS is active low.
SRAM Output Enable (GS). The Output Enable
gates the outputs through the data buffers during
a read operation of the SRAM memory. GS is ac-
tive low.
SRAM Upper Byte Enable (UBS). The
Upper
Byte Enable enables the upper bytes for SRAM
(DQ8-DQ15). UBS is active low.
SRAM Lower Byte Enable (LBS). The
Lower
Byte Enable enables the lower bytes for SRAM
(DQ0-DQ7). LBS is active low.
VDDF Supply Voltage (2.7V to 3.3V). VDDF pro-
vides the power supply to the internal core of the
Flash Memory device. It is the main power supply
for all operations (Read, Program and Erase).
VDDQF and VDDS Supply Voltage (2.7V to 3.3V).
VDDQF provides the power supply for the Flash
memory I/O pins and VDDS provides the power
supply for the SRAM control pins. This allows all
Outputs to be powered independently of the Flash
core power supply, VDDF. VDDQF can be tied to
VDDS
VPPF Program Supply Voltage. VPPF is both a
control input and a power supply pin for the Flash
memory. The two functions are selected by the
voltage range applied to the pin. The Supply Volt-
age VDDF and the Program Supply Voltage VPPF
can be applied in any order.
If VPPF is kept in a low voltage range (0V to 3.6V)
VPPF is seen as a control input. In this case a volt-
age lower than VPPLK gives an absolute protection
against program or erase, while VPPF > VPP1 en-
ables these functions (see Table 15, DC Charac-
teristics for the relevant values). VPPF is only
sampled at the beginning of a program or erase; a
change in its value after the operation has started
does not have any effect on Program or Erase,
however for Double or Quadruple Word Program
the results are uncertain.
If VPPF is in the range 11.4V to 12.6V it acts as a
power supply pin. In this condition VPPF must be
stable until the Program/Erase algorithm is com-
pleted (see Table 17 and 18).


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