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ADSP-BF539BBCZ-5F4 Datasheet(PDF) 3 Page - Analog Devices |
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ADSP-BF539BBCZ-5F4 Datasheet(HTML) 3 Page - Analog Devices |
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3 / 60 page  ADSP-BF539/ADSP-BF539F Rev. A | Page 3 of 60 | February 2008 GENERAL DESCRIPTION The ADSP-BF539/ADSP-BF539F processors are members of the Blackfin ® family of products, incorporating the Analog Devices, Inc./Intel Micro Signal Architecture (MSA). Blackfin processors combine a dual-MAC, state-of-the-art signal pro- cessing engine, the advantages of a clean, orthogonal RISC-like microprocessor instruction set, and single-instruction, multi- ple-data (SIMD) multimedia capabilities into a single instruction set architecture. The ADSP-BF539/ADSP-BF539F processors are completely code compatible with other Blackfin processors, differing only with respect to performance, peripherals, and on-chip memory. Specific performance, peripherals, and memory configurations are shown in Table 1 on Page 3. By integrating a rich set of industry-leading system peripherals and memory, Blackfin processors are the platform of choice for next generation applications that require RISC-like program- mability, multimedia support, and leading edge signal processing in one integrated package. LOW POWER ARCHITECTURE Blackfin processors provide world class power management and performance. Blackfin processors are designed in a low power and low voltage design methodology and feature dynamic power management, the ability to vary both the voltage and fre- quency of operation to significantly lower overall power consumption. Varying the voltage and frequency can result in a substantial reduction in power consumption, compared with simply varying the frequency of operation. This translates into longer battery life and lower heat dissipation. AUTOMOTIVE PRODUCTS Some ADSP-BF539/ADSP-BF539F models are available for automotive applications with controlled manufacturing. Note that these special models may have specifications that differ from the general release models. For information on which models are available for automotive applications, see “Ordering Guide” on page 60. SYSTEM INTEGRATION The ADSP-BF539/ADSP-BF539F processors are highly inte- grated system-on-a-chip solutions for the next generation of industrial and automotive applications including audio and video signal processing. By combining advanced memory con- figurations, such as on-chip flash memory, with industry- standard interfaces with a high performance signal processing core, users can develop cost-effective solutions quickly without the need for costly external components. The system peripherals include a MOST Network Media Transceiver (MXVR), three UART ports, three SPI ports, four serial ports (SPORT), one CAN interface, two 2-wire interfaces (TWI), four general-pur- pose timers (three with PWM capability), a real-time clock, a watchdog timer, a parallel peripheral interface, general-purpose I/O, and general-purpose flag pins. ADSP-BF539/ADSP-BF539F PROCESSOR PERIPHERALS The ADSP-BF539/ADSP-BF539F processors contain a rich set of peripherals connected to the core via several high bandwidth buses, providing flexibility in system configuration as well as excellent overall system performance (see Figure 1 on Page 1). The general-purpose peripherals include functions such as UART, timers with PWM (pulse-width modulation) and pulse measurement capability, general-purpose flag I/O pins, a real- time clock, and a watchdog timer. This set of functions satisfies a wide variety of typical system support needs and is augmented by the system expansion capabilities of the device. In addition to these general-purpose peripherals, the ADSP-BF539/ADSP- BF539F processors contain high speed serial and parallel ports for interfacing to a variety of audio, video, and modem codec functions. An MXVR transceiver transmits and receives audio and video data and control information on a MOST automotive multimedia network. A CAN 2.0B controller is provided for automotive control networks. An interrupt controller manages interrupts from the on-chip peripherals or external sources. And power management control functions tailor the perfor- mance and power characteristics of the processor and system to many application scenarios. All of the peripherals, except for general-purpose I/O, CAN, TWI, real-time clock, and timers, are supported by a flexible DMA structure. There are also four separate memory DMA channels dedicated to data transfers between the processor’s Table 1. Processor Features Feature ADSP-BF539 ADSP-BF539F4 ADSP-BF539F8 SPORTs 4 4 4 UARTs 3 3 3 SPI 3 3 3 TWI 2 2 2 CAN 1 1 1 MXVR 1 1 1 PPI 1 1 1 Instruction SRAM/Cache 16K bytes 16K bytes 16K bytes Instruction SRAM 64K bytes 64K bytes 64K bytes Data SRAM/Cache 32K bytes 32K bytes 32K bytes Data SRAM 32K bytes 32K bytes 32K bytes Scratchpad 4K bytes 4K bytes 4K bytes Flash Not applicable 256K 16-bit 512K 16-bit Maximum Speed Grade 533 MHz 1066 MMACS 533 MHz 1066 MMACS 533 MHz 1066 MMACS Package Option BC-316 BC-316 BC-316 |
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