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ADSP-BF539BBCZ-5F4 Datasheet(PDF) 1 Page - Analog Devices |
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ADSP-BF539BBCZ-5F4 Datasheet(HTML) 1 Page - Analog Devices |
1 / 60 page Blackfin and the Blackfin logo are registered trademarks of Analog Devices, Inc. Blackfin Embedded Processor ADSP-BF539/ADSP-BF539F Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2008 Analog Devices, Inc. All rights reserved. FEATURES 1.0 V to 1.25 V core VDD with on-chip voltage regulation 3.0 V to 3.3 V I/O VDD Up to 3.3 V tolerant I/O with specific 5 V tolerant pins 316-ball Pb-free CSP_BGA package Up to 533 MHz high performance Blackfin processor Two 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs, 40-bit shifter RISC-like register and instruction model for ease of programming and compiler friendly support Advanced debug, trace, and performance monitoring MEMORY 148K bytes of on-chip memory: 16K bytes of instruction SRAM/cache 64K bytes of instruction SRAM 32K bytes of data SRAM 32K bytes of data SRAM/cache 4K bytes of scratchpad SRAM 512K 16-bit or 256K 16-bit flash memory (ADSP-BF539F only) Memory management unit providing memory protection External memory controller with glueless support for SDRAM, SRAM, flash, and ROM Flexible memory booting options from SPI and external memory PERIPHERALS Parallel peripheral interface (PPI), supporting ITU-R 656 video data formats 4 dual-channel, full-duplex synchronous serial ports, sup- porting 16 stereo I 2S channels 2 DMA controllers supporting 26 peripheral DMAs 4 memory-to-memory DMAs Controller area network (CAN) 2.0B controller Media transceiver (MXVR) for connection to a MOST network 3 SPI-compatible ports Three 32-bit timer/counters with PWM support 3 UARTs with support for IrDA 2 TWI controllers compatible with I2C industry standard Up to 38 general-purpose I/O pins (GPIO) Up to 16 general-purpose flag pins (GPF) Real-time clock, watchdog timer, and 32-bit core timer On-chip PLL capable of 0.5 to 64 frequency multiplication Debug/JTAG interface Figure 1. Functional Block Diagram UART0 SPORT0-1 WATCHDOG TIMER RTC SPI0 TIMER0-2 PPI SPI1-2 SPORT2-3 UART1-2 GPIO PORT F GPIO PORT D GPIO PORT C GPIO PORT E EXTERNAL PORT FLASH, SDRAM CONTROL BOOT ROM JTAG TEST AND EMULATION VOLTAGE REGULATOR DMA CONTROLLER 0 L1 INSTRUCTION MEMORY L1 DATA MEMORY DMA CONTROLLER1 B INTERRUPT CONTROLLER PERIPHERAL ACCESS BUS DMA CORE BUS 0 DMA EXTERNAL BUS 1 TWI0-1 CAN 2.0B MXVR 512kB OR 1MB FLASH MEMORY (ADSP-BF539F ONLY) DMA CORE BUS 1 DMA EXTERNAL BUS 0 DMA CORE BUS 2 16 |
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