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FEATURES

DB, DGV, DW, NS, OR PW PACKAGE

(TOP VIEW)

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24

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17

16

15

14

13

OE

1D

2D

3D

4D

5D

6D

7D

8D

9D

10D

GND

1Q

2Q

3Q

4Q

5Q

6Q

7Q

8Q

9Q

10Q

CLK

DESCRIPTION/ORDERING INFORMATION

SN74LVC821A

10-BIT BUS-INTERFACE FLIP-FLOP

WITH 3-STATE OUTPUTS

SCAS304J – MARCH 1993 – REVISED FEBRUARY 2005

•

Operates From 1.65 V to 3.6 V

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Inputs Accept Voltages to 5.5 V

•

•

•

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Supports Mixed-Mode Signal Operation on All

Ports (5-V Input/Output Voltage With

•

Operation

•

Latch-Up Performance Exceeds 250 mA Per

JESD 17

•

ESD Protection Exceeds JESD 22

– 2000-V Human-Body Model (A114-A)

The SN74LVC821A features 3-state outputs designed specifically for driving highly capacitive or relatively

low-impedance loads. This device is particularly suitable for implementing wider buffer registers, I/O ports,

bidirectional bus drivers with parity, and working registers.

The ten flip-flops are edge-triggered D-type flip-flops. On the positive transition of the clock (CLK) input, the

device provides true data at the Q outputs.

A buffered output-enable (OE) input can be used to place the ten outputs in either a normal logic state (high or

low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the

bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines

without interface or pullup components.

OE does not affect the internal operations of the latch. Previously stored data can be retained or new data can

be entered while the outputs are in the high-impedance state.

ORDERING INFORMATION

ORDERABLE PART NUMBER

TOP-SIDE MARKING

Tube of 25

SN74LVC821ADW

SOIC – DW

LVC821A

Reel of 2000

SN74LVC821ADWR

SOP – NS

Reel of 2000

SN74LVC821ANSR

LVC821A

SSOP – DB

Reel of 2000

SN74LVC821ADBR

LC821A

–40

°C to 85°C

Tube of 60

SN74LVC821APW

TSSOP – PW

Reel of 2000

SN74LVC821APWR

LC821A

Reel of 250

SN74LVC821APWT

TVSOP – DGV

Reel of 2000

SN74LVC821ADGVR

LC821A

(1)

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at

www.ti.com/sc/package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Copyright © 1993–2005, Texas Instruments Incorporated

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.