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ICS854054AGLFT Datasheet(PDF) 7 Page - Integrated Circuit Systems |
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ICS854054AGLFT Datasheet(HTML) 7 Page - Integrated Circuit Systems |
7 / 13 page 854054AG www.icst.com/products/hiperclocks.html REV. A MARCH 29, 2006 7 Integrated Circuit Systems, Inc. ICS854054 4:1 DIFFERENTIAL-TO-LVDS CLOCK MULTIPLEXER APPLICATION INFORMATION WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS Figure 1 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = V DD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and V DD= 3.3V, V_REF should be 1.25V and R2/R1 = 0.609. VDD R2 1K V_REF C1 0.1u R1 1K Single Ended Clock Input PCLK nPCLK INPUTS: PCLK/nPCLK INPUT: For applications not requiring the use of a differential input, both the PCLK and nPCLK pins can be left floating. Though not required, but for additional protection, a 1k Ω resister can be tied from PCLK to ground. SELECT PINS: All select pins have internal pull-ups and pull-downs; additional resistance is not required but can be added for additional protection. A 1k Ω resister can be used. RECOMMENDATIONS FOR UNUSED INPUT PINS |
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