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M27C160-120S6TR Datasheet(HTML) 4 Page - STMicroelectronics

Part No. M27C160-120S6TR
Description  16 Mbit 2Mb x8 or 1Mb x16 UV EPROM and OTP EPROM
Download  19 Pages
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Maker  STMICROELECTRONICS [STMicroelectronics]
Homepage  http://www.st.com
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M27C160-120S6TR Datasheet(HTML) 4 Page - STMicroelectronics

 
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M27C160
4/19
DEVICE OPERATION
The operating modes of the M27C160 are listed in
the Operating Modes Table. A single power supply
is required in the read mode. All inputs are TTL
compatible except for VPP and 12V on A9 for the
Electronic Signature.
Read Mode
The M27C160 has two organisations, Word-wide
and Byte-wide. The organisation is selected by the
signal level on the BYTEVPP pin. When BYTEVPP
is at VIH the Word-wide organisation is selected
and the Q15A–1 pin is used for Q15 Data Output.
When the BYTEVPP pin is at VIL the Byte-wide or-
ganisation is selected and the Q15A–1 pin is used
for the Address Input A–1. When the memory is
logically regarded as 16 bit wide, but read in the
Byte-wide organisation, then with A–1 at VIL the
lower 8 bits of the 16 bit data are selected and with
A–1 at VIH the upper 8 bits of the 16 bit data are
selected.
The M27C160 has two control functions, both of
which must be logically active in order to obtain
data at the outputs. In addition the Word-wide or
Byte- wide organisation must be selected.
Chip Enable (E) is the power control and should be
used for device selection. Output Enable (G)isthe
output control and should be used to gate data to
the output pins independent of device selection.
Assuming that the addresses are stable, the ad-
dress access time (tAVQV) is equal to the delay
from E to output (tELQV). Data is available at the
output after a delay of tGLQV from the falling edge
of G, assuming that E has been low and the ad-
dresses have been stable for at least tAVQV-tGLQV.
Table 5. AC Measurement Conditions
High Speed
Standard
Input Rise and Fall Times
≤ 10ns
≤ 20ns
Input Pulse Voltages
0 to 3V
0.4V to 2.4V
Input and Output Timing Ref. Voltages
1.5V
0.8V and 2V
Figure 5. AC Testing Input Output Waveform
AI01822
3V
High Speed
0V
1.5V
2.4V
Standard
0.4V
2.0V
0.8V
Figure 6. AC Testing Load Circuit
AI01823B
1.3V
OUT
CL
CL = 30pF for High Speed
CL = 100pF for Standard
CL includes JIG capacitance
3.3k
1N914
DEVICE
UNDER
TEST
Table 6. Capacitance (1) (TA = 25 °C,f= 1 MHz)
Note: 1. Sampled only, not 100% tested.
Symbol
Parameter
Test Condition
Min
Max
Unit
CIN
Input Capacitance (except BYTEVPP)VIN =0V
10
pF
Input Capacitance (BYTEVPP)VIN =0V
120
pF
COUT
Output Capacitance
VOUT =0V
12
pF


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