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M29W641DU10N6F Datasheet(PDF) 5 Page - STMicroelectronics |
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M29W641DU10N6F Datasheet(HTML) 5 Page - STMicroelectronics |
5 / 42 page 5/42 M29W641DH, M29W641DL, M29W641DU SUMMARY DESCRIPTION The M29W641D is a 64 Mbit (4Mb x16) non-vola- tile memory that can be read, erased and repro- grammed. These operations can be performed using a single, low voltage, 2.7V to 3.6V VCC sup- ply for the circuitry and a 1.8V to 3.6V VCCQ supply for the Input/Output pins. An optional 12 V VPP power supply is provided to speed up customer programming. On power-up the memory defaults to its Read mode where it can be read in the same way as a ROM or EPROM. The highest address block of the M29W641DH or the lowest address block of the M29W641DL can be protected from accidental programming or era- sure using the WP pin (if WP = VIL). The M29W641DU does not feature the WP pin. Each block can be erased independently so it is possible to preserve valid data while old data is erased. The blocks can be protected to prevent accidental Program or Erase commands from modifying the memory. Program and Erase com- mands are written to the Command Interface of the memory. An on-chip Program/Erase Controller simplifies the process of programming or erasing the memory by taking care of all of the special op- erations that are required to update the memory contents. The end of a program or erase operation can be detected and any error conditions identi- fied. The command set required to control the memory is consistent with JEDEC standards. The M29W641D has an extra block, the Extended Block, (of 32 KWords) that can be accessed using a dedicated command. The Extended Block can be protected and so is useful for storing security information. However the protection is not revers- ible, once protected the protection cannot be un- done. Chip Enable, Output Enable and Write Enable sig- nals control the bus operation of the memory. They allow simple connection to most micropro- cessors, often without additional logic. The memory is offered in a 48-pin TSOP package (M29W641DL and M29W641DH) or in a 63-ball TF- BGA package (M29W641DU). All devices are deliv- ered with all the bits erased (set to 1). Figure 2. Logic Diagram Table 1. Signal Names A0-A21 Address Inputs DQ0-DQ7 Data Inputs/Outputs DQ8- DQ15 Data Inputs/Outputs E Chip Enable G Output Enable W Write Enable RP Reset/Block Temporary Unprotect (M29W641DH and M29W641DL only) RB Ready/Busy Output (M29W641DU only) WP Write Protect VCC Supply Voltage VCCQ Supply Voltage for Input/Output VPP Supply Voltage for Fast Program (optional) VSS Ground AI06697b 22 A0-A21 W DQ0-DQ15 VCC M29W641D E VSS 16 G RP VPP WP VCCQ RB |
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