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A6278ELPTR-T Datasheet(PDF) 6 Page - Allegro MicroSystems |
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A6278ELPTR-T Datasheet(HTML) 6 Page - Allegro MicroSystems |
6 / 18 page Serial-Input, Constant-Current Latched LED Drivers with Open LED Detection A6278 and A6279 6 Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com A6278, n = 7 A6279, n = 15 CLOCK OUTPUT ENABLE LATCH ENABLE CLOCK OUTPUT ENABLE LATCH ENABLE CLOCK OUTPUT ENABLE SERIAL DATA OUT Don't Care tlow thigh tSU(OE1) tSU(LE1) tH(LE1) tW(OE1) 1 1 2 3 tH(OE1) tlow thigh 12 3 tSU(OE1) tH(OE1) SDO n SDO n-1 SDO n-2SDO 0 (A) To enter LED OCD mode, a minimum of one CLOCK pulse is required after LATCH ENABLE is brought back low. (B) To output the latched error code, OUTPUT ENABLE must be held low a minimum of 3 CLOCK cycles. (C) When returning to Normal mode, a minimum of three CLOCK pulses is required after OUTPUT ENABLE is brought back high. Normal Mode Timing Requirements LED Open Circuit Detection (Test) Mode Timing Requirements 01 n CLOCK A6278, n = 7 A6279, n = 15 SERIAL DATA IN SDI n SDI n-1 SDI 0 Don't Care SDO n SERIAL DATA OUT LATCH ENABLE OUTPUT ENABLE OUT0 Don't Care OUT1 OUTn Don't Care Don't Care t low t high t SU(D) tH(D) t p(DO) t SU(LE) tH(LE) t W(OE) tW(OE) t P(OE) t D t D(Total) t P(OE) t D t D(Total) t SU(OE) Logic Levels: VDD and GND Logic Levels: VDD and GND |
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